may4
swapforth
may4 | swapforth | |
---|---|---|
8 | 5 | |
35 | 272 | |
- | - | |
1.3 | 4.6 | |
about 1 year ago | 5 months ago | |
Forth | Forth | |
MIT License | BSD 3-clause "New" or "Revised" License |
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may4
- Celebrating Star Wars Day with some Forth code May the Forth be with you
- Star Wars Day: May the Forth Be with You
- May the Forth Be with You
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Forth: Stack-Manipulation Operators
Incidentally, a couple of weeks ago I wrote a tiny Star Wars-themed Forth program to celebrate Star Wars Day: https://github.com/susam/may4
Forth brings back the fun in computing for me that I once experienced when I began learning to code with Logo. Simple, distraction-free, and fun!
"I think that it's extraordinarily important that we in computer science keep fun in computing. When it started out, it was an awful lot of fun. Of course, the paying customers got shafted every now and then, and after a while we began to take their complaints seriously. We began to feel as if we really were responsible for the successful, error-free perfect use of these machines. I don't think we are. I think we're responsible for stretching them, setting them off in new directions, and keeping fun in the house. I hope the field of computer science never loses its sense of fun." -- Alan J. Perlis
- Celebrating Star Wars Day with some Forth code! May the Forth be with you!
- Some Star Wars-themed Forth programming. May the Forth be with you
- Celebrate Star Wars Day with some Forth code. May the Forth be with you!
swapforth
- Making my own forth implementation
- FPGAs for interpreted programming languages?
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How many LUT for an 8 bit CPU?
Thanks! Found the port of this to the board I want :) https://github.com/jamesbowman/swapforth/tree/master/j1a
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The RISC Deprogrammer
It's a standard thing to do in EE curricula; you normally do it in a one-semester class, and there are literally thousands of open-source synthesizable CPU cores on GitHub now.
To take two examples to show that designing a CPU is less work than writing a novel:
- Chuck Thacker's "A Tiny Computer", fairly similar to the Nova, is a page and a half of synthesizable Verilog; it runs at 66 MHz in 200 LUTs of a Virtex-5: https://www.cl.cam.ac.uk/~swm11/examples/bluespec/Tiny3/Thac...
- James Bowman's J1A is more like Chuck Moore's MuP21 and is about three pages of synthesizable Verilog: https://github.com/jamesbowman/swapforth/blob/master/j1a/ver... and https://github.com/jamesbowman/swapforth/blob/master/j1a/ver.... You can build it with Claire Wolf's iCEStorm (yosys, etc.) and run it on any but Lattice's tiniest FPGAs; it takes up 1162 4-input LUTs.
I haven't quite done it myself. Last time I played https://nandgame.com/ it took me a couple of hours to play through the hardware design levels. But that's not really "design" in the sense of defining the instruction set (which is also kind of Nova-like), thinking through state machine design, and trying different pipeline depths; you're mostly just doing the kind of logic minimization exercises you'd normally delegate to yosys.
In https://github.com/kragen/calculusvaporis I designed a CPU instruction set, wrote a simulator for it, wrote and tested some simple programs, designed a CPU at the RTL level, and sketched out gate-level logic designs to get an estimate of how big it would be. But I haven't simulated the RTL to verify it, written it down in an HDL, or breadboarded the circuit, so I'm reluctant to say that this qualifies as "designing a single CPU" either.
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The J1 Forth CPU
Also worth checking is the Swapforth Github repository.