litmus-tests-riscv
RISC-V architecture concurrency model litmus tests (by litmus-tests)
force-riscv
Instruction Set Generator initially contributed by Futurewei (by openhwgroup)
| litmus-tests-riscv | force-riscv | |
|---|---|---|
| 2 | 1 | |
| 62 | 234 | |
| - | 4.7% | |
| 3.6 | 3.6 | |
| 8 months ago | 7 months ago | |
| Assembly | C++ | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
litmus-tests-riscv
Posts with mentions or reviews of litmus-tests-riscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-03-06.
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Temporal Fuzzing I: Memory Models (2021)
It would be interesting to see this interact with the lower-level ISA memory model work in diy, litmus, etc. Could you validate your ISA memory models against the generated litmus tests in https://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test6.pdf, https://github.com/litmus-tests/litmus-tests-riscv?
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Areas to contribute in RISC-V RTL verification
Or extending work here on the diy / litmus stuff: https://github.com/litmus-tests/litmus-tests-riscv
force-riscv
Posts with mentions or reviews of force-riscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-03-06.
-
Areas to contribute in RISC-V RTL verification
dynamic random instruction generator for riscv
What are some alternatives?
When comparing litmus-tests-riscv and force-riscv you can also consider the following projects:
sail-riscv - Sail RISC-V model
riscv-dv - Random instruction generator for RISC-V processor verification
riscv-config - RISC-V Configuration Validator