ecma6-forth
swapforth
| ecma6-forth | swapforth | |
|---|---|---|
| 1 | 5 | |
| 13 | 271 | |
| - | - | |
| 0.0 | 4.6 | |
| 4 months ago | 4 months ago | |
| Forth | Forth | |
| - | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ecma6-forth
-
What the hell is Forth? (2019)
I didn't really understand forth till I tried implementing eforth in c.
https://github.com/tehologist/forthkit
Managed to write a compiler/interpreter that could understand enough forth to implement the entire system. Less than 500 lines and only uses stdio.h and compiles using TCC
https://bellard.org/tcc/
That was so much fun I built a second one in under 300 lines of javascript for experimenting with canvas api in web browser. Single file doesn't require a server, you can drag and drop code onto text window.
https://github.com/tehologist/ecma6-forth
Runs standalone, I want to get back to it again.
swapforth
- Making my own forth implementation
- FPGAs for interpreted programming languages?
-
How many LUT for an 8 bit CPU?
Thanks! Found the port of this to the board I want :) https://github.com/jamesbowman/swapforth/tree/master/j1a
-
The RISC Deprogrammer
It's a standard thing to do in EE curricula; you normally do it in a one-semester class, and there are literally thousands of open-source synthesizable CPU cores on GitHub now.
To take two examples to show that designing a CPU is less work than writing a novel:
- Chuck Thacker's "A Tiny Computer", fairly similar to the Nova, is a page and a half of synthesizable Verilog; it runs at 66 MHz in 200 LUTs of a Virtex-5: https://www.cl.cam.ac.uk/~swm11/examples/bluespec/Tiny3/Thac...
- James Bowman's J1A is more like Chuck Moore's MuP21 and is about three pages of synthesizable Verilog: https://github.com/jamesbowman/swapforth/blob/master/j1a/ver... and https://github.com/jamesbowman/swapforth/blob/master/j1a/ver.... You can build it with Claire Wolf's iCEStorm (yosys, etc.) and run it on any but Lattice's tiniest FPGAs; it takes up 1162 4-input LUTs.
I haven't quite done it myself. Last time I played https://nandgame.com/ it took me a couple of hours to play through the hardware design levels. But that's not really "design" in the sense of defining the instruction set (which is also kind of Nova-like), thinking through state machine design, and trying different pipeline depths; you're mostly just doing the kind of logic minimization exercises you'd normally delegate to yosys.
In https://github.com/kragen/calculusvaporis I designed a CPU instruction set, wrote a simulator for it, wrote and tested some simple programs, designed a CPU at the RTL level, and sketched out gate-level logic designs to get an estimate of how big it would be. But I haven't simulated the RTL to verify it, written it down in an HDL, or breadboarded the circuit, so I'm reluctant to say that this qualifies as "designing a single CPU" either.
-
The J1 Forth CPU
Also worth checking is the Swapforth Github repository.