eater-sap-1-improvements VS 8-bit-computer

When I figure out why the "voice" is unintelligible, I will be certainly posting all the details and making a video as I have done with my prior projects for this computer. Subscribe to my YouTube or follow my GitHub repository to get alerts.

The details of my design evolution from the Eater SAP-1 to what you see here are documented at my GitHub repository. You can also watch video overviews if each improvement project at my YouTube channel, the I haven’t yet made the video for the ALU that’s enabling multiplication and division through bit shifting. That’s only at my GitHub at the moment.

Ha ... yeah, it was overkill, but the 32K was just sitting there unused. If you check out my code for the prime number calculation, you'll see the stack is well used. However, I haven't cracked the 256 byte depth yet.

I am using the ATF22V10C in my build. Works great. I’ve made some notes on programming them here: https://github.com/michaelkamprath/eater-sap-1-improvements/tree/advanced-alu/advanced-alu/pld-files

I’ve done a number of upgrades myself. They are documented here: https://github.com/michaelkamprath/eater-sap-1-improvements

Here's the write button. https://i.imgur.com/N3WgqR9.jpg I've inverted it from a pull-up switch to GND, to a pull-down switch to VCC, using Michael Kamprath's improvement recommendations found at https://github.com/michaelkamprath/eater-sap-1-improvements/tree/main/improving-reliability-of-ram-module

This iteration on the CPU focused on implementing a 8-bit instruction register. However, doing this required me to rethink many parts of the computer, notably the memory map and the control logic. Details on what I accomplished in this project can be found in my GitHub repository: https://github.com/michaelkamprath/eater-sap-1-improvements/tree/main/instruction-register-8-bit

If you want to read up on what I am doing here before I create a video on it, I have documented everything here (though there are a few bits I still need to document).

You can check out the current state of my design on my ram-upgrade branch in my GitHub repository. It's still a work in progress, so don't yet expect the same level of documentation or completeness my other modules have.

Here's a nice collection of programs i found: https://github.com/blurpy/8-bit-computer/tree/master/programs (thanks, u/blurpy1 !)

https://github.com/blurpy/8-bit-computer/blob/master/issues.md kinda explained but i didnt exactly follow it the way they solved it, kinda did my own thing

Hello! This could linked to bouncing noise on the memory write line caused by the switch as it transitions from one state to the other. The 104 cap solution described in the 'RAM mode switch changes memory content' section of this post might work for you.

follow this git repo for more solutions to common problems https://github.com/blurpy/8-bit-computer/blob/master/issues.md

Hello! There is a known memory corruption issue with the run/prog switch when it transitions. Take a peek at the "RAM mode switch changes memory content" section of this post. The solution in there may work for you.

Hello! Had the same exact same issue. Turned out to be a spike on the reset line when there were a lot of state transitions on the bus. Putting a cap on the reset pin of the A register, as explained in the 'A Register Resetting' section of this post did it for me. Might be worth trying.