busybox
riscv-isa-manual
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Dockerfile | TeX | |
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busybox
- The Awk Programming Language, Second Edition
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This would have made my life so much easier in the beginning....
A majority of routers are already based on the Linux kernel. Many are just BusyBox. The most common Linux firewalls are iptables and nftables. With the latter being the most popular one due to being around longer. They are really fine grained and powerful.
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kubectl run --command vs -- arguments
As Busybox DockerFile does not contain any EntryPoint(https://github.com/docker-library/busybox/blob/master/musl/Dockerfile), so arguments specified in the kubectl command will only be used, so the command will look like:
- Emacs standing alone on a Linux Kernel
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So Im working on making my own OS from scratch. Im using a linux based os for reverse engineering but I need help in understanding how to use the tools that are in rar/zip files. If anyone can direct me to some tutorials or resources to read that would be a big help.
https://www.kernel.org/doc/Documentation/arm64/booting.rst This was my guiding light for a project a while back. It describes what Linux expects "time zero" looks like for the system; whatever operating system is going to boot needs that kind of contract between the boot environment and its own entry point. You can develop a lightweight linux-based OS with that document and a package like https://busybox.net/
- The amount of times I have accidentally done this...
- BusyBox 1.36.0
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MIT
UUTILS, musl libc, BusyBox , etc.
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Do you think Linux will become more supported and eventually be able to play every game that windows can? If so, how far in the future?
For libc, we have musl as an alternate implementation. For most coreutils, we have busybox and the BSD coreutils. For desktop environments, you can use something like xfce.
riscv-isa-manual
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The Improved RISC-V Specification (latest WIP draft)
https://github.com/riscv/riscv-isa-manual/releases
Regarding the recent "How to improve the RISC-V specification" post [0], I just wanted to point out, that the latest draft manual is already a great improvement. (see link above)
It includes a lot of the newly ratified extensions: bitmanip,zicond,vector,vector crypto, ...
And there are a bunch of included SAIL definitions for bitmanip and zicond, but other instructions are still missing the SAIL code. Most notably, the SAIL definitions from the RV32I/RV64I base isa are also missing.
I asked for the further SAIL integration plans here: https://github.com/riscv/riscv-isa-manual/issues/1369
Here is an example SAIL snippet from cpopw:
let bitcount = 0;
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How to improve the RISC-V specification
I encourage you to look at the newest isa manual draft on github: https://github.com/riscv/riscv-isa-manual/releases
It includes the more recently extensions, and e.g. the bitmanip instructions all have associated pseudo code.
Here is e.g. the code for cpopw:
let bitcount = 0;
- Need help with designing a basic RISC V processor?
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The legend of “x86 CPUs decode instructions into RISC form internally”
I tried searching the spec [1] for "overflow" and here is what it says at page 17:
> We did not include special instruction-set support for overflow checks on integer arithmetic operations in the base instruction set, as many overflow checks can be cheaply implemented using RISC-V branches.
> For general signed addition, three additional instructions after the addition are required
Is this "cheap", replacing 1 instruction with four? According to some old mainframe era research (cannot find link now), addition is the most often used instruction and they suggest that we should replace each one with four?
Their "rationale" is not rational at all. It doesn't make sense.
Overflow check should be free (no additional instructions required), otherwise we will see the same story we have seen for last 50 years: compiler writers do not want to implement checks because they are expensive; language designers do not want to use proper arithmetic because it is expensive. As a result, there will be errors and vulnerabilities. A vicious circle.
[1] https://github.com/riscv/riscv-isa-manual/releases/download/...
- 64-bit Arm ∩ 64-bit RISC V
- Beginner question: F extension
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Riscv Ghidra Instruction Manual
Why not use the actual release PDF instead from their github? https://github.com/riscv/riscv-isa-manual
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How would I go about designing an 8-bit RISC-V CPU? Is it possible?
https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf Part 2
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Have to convert a C language code into RISC-V MIPS
If you don't want to cheat then read the RISC-V ISA manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
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How does a computer understand machine language?
Yeah you are on the right track. Processors are designed on top of an Instruction Set Architecture (ISA). For an example you can look on top of the RISC-V specifications:https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf (possible PDF download)
What are some alternatives?
hush - Hush is a unix shell based on the Lua programming language
riscv-elf-psabi-doc - A RISC-V ELF psABI Document
u-boot - "Das U-Boot" Source Tree
riscv-emulator-docker-image
toybox - toybox
amaranth - A modern hardware definition language and toolchain based on Python
buildroot - Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
cage - A Wayland kiosk
vroom - VRoom! RISC-V CPU
barebox - The barebox bootloader - Mirror of ssh://[email protected]/barebox
open-source-cs - Video discussing this curriculum: