derzforth
jonesforth_riscv
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| derzforth | jonesforth_riscv | |
|---|---|---|
| 2 | 3 | |
| 36 | 52 | |
| - | - | |
| 4.0 | 1.8 | |
| 3 months ago | over 3 years ago | |
| Assembly | Assembly | |
| MIT License | - |
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derzforth
jonesforth_riscv
- Jonesforth ported to RISC-V
-
Jonesforth Port to RISC-V
Uncompressed RISC-V instructions are 4 bytes. Compressed instructions are 2 bytes. Without some completely unanticipated extension that goes against the current design, there will be no way to make a 3-byte instruction sequence for RISC-V.
[0]https://github.com/jjyr/jonesforth_riscv/blob/master/jonesfo...
What are some alternatives?
TaliForth2 - A Subroutine Threaded Code (STC) ANS-like Forth for the 65c02
ti84-forth - A Forth implementation for the TI-84+ calculator.
lbForth - Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
jonesforth - Mirror of JONESFORTH
bronzebeard - Minimal assembler and ecosystem for bare-metal RISC-V development
rv51 - A RISC-V emulator for the 8051 (MCS-51) microcontroller.
riscv-hello-asm - Bare metal RISC-V assembly hello world
kestrel - The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.
stm8ef - STM8 eForth - a user friendly Forth for simple µCs with docs