jonesforth_riscv
riscv-hello-asm
| jonesforth_riscv | riscv-hello-asm | |
|---|---|---|
| 3 | 1 | |
| 52 | 40 | |
| - | - | |
| 1.8 | 0.0 | |
| over 3 years ago | over 2 years ago | |
| Assembly | Assembly | |
| - | GNU General Public License v3.0 or later |
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jonesforth_riscv
- Jonesforth ported to RISC-V
-
Jonesforth Port to RISC-V
Uncompressed RISC-V instructions are 4 bytes. Compressed instructions are 2 bytes. Without some completely unanticipated extension that goes against the current design, there will be no way to make a 3-byte instruction sequence for RISC-V.
[0]https://github.com/jjyr/jonesforth_riscv/blob/master/jonesfo...
riscv-hello-asm
-
Jonesforth Port to RISC-V
This works well enough to compile my hello-world example (available here[1]) but I'd like to use that `fp` register naming...
[0]: https://nixos.wiki/wiki/Cross_Compiling
[1]: https://github.com/noteed/riscv-hello-asm
What are some alternatives?
ti84-forth - A Forth implementation for the TI-84+ calculator.
jonesforth - Mirror of JONESFORTH
RISC-V-Guide - RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
lbForth - Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
lz4_rv32i_decode - LZ4 decoder in assembly for RiscV RV32IC
derzforth - Bare-metal Forth implementation for RISC-V
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
kestrel - The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.
stm8ef - STM8 eForth - a user friendly Forth for simple µCs with docs
TaliForth2 - A Subroutine Threaded Code (STC) ANS-like Forth for the 65c02