riscv
Container image for RISC-V (by codewars)
marvelos
Marvelous RISC-V Operating System, by donaldsebleung (by DonaldKellett)
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv
Posts with mentions or reviews of riscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-09-10.
-
Getting started with OSDev on RISC-V
Playing around with userspace RISC-V assembly in multiarch containers with QEMU user mode emulation
marvelos
Posts with mentions or reviews of marvelos.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-19.
-
My RISC-V OSDev journey, so far
GitHub repository: https://github.com/DonaldKellett/marvelos
-
Getting started with OSDev on RISC-V
Over the past few days, I've managed to implement a rudimentary RISC-V operating system kernel in C that does little more than print stuff to the serial console. Nevertheless, I did my best to structure the project to facilitate development in the mid- to long-term. The project template which I'll build upon going forward is released on GitHub as v0.0.1 of maRVelOS code-named "Meaty Skeleton", so if you're also interested in RISC-V and open hardware as a programmer, feel free to follow along!