VHDL-Issues
By IEEE-P1076
RedPitaya-FPGA
Repository for FPGA projects (by RedPitaya)
| VHDL-Issues | RedPitaya-FPGA | |
|---|---|---|
| 11 | 1 | |
| - | 28 | |
| - | - | |
| - | 8.1 | |
| - | about 2 months ago | |
| Tcl | ||
| - | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
VHDL-Issues
Posts with mentions or reviews of VHDL-Issues.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-02-02.
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What would be your go-to solution for configurable number of entity's output signals? (VHDL)
Not possible until VHDL 2019 using conditional analysis (basically VHDL pre-processor). This is supported by the newest intel Pro tools and most paid for simulators. A better version, without having to use conditional analysis, is proposed for VHDL 202X : https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/205
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How to create a register array in VHDL in which each entry in the array has input and outputting on the same cycle, behaves as a register, and is coded as an entry in an array?
You are confusing all sorts of VHDL terms. my_array is simply an array object, it has no ports. Ports exist on an entity. Vhdl has no direct knowledge of underlying hardware, hence register_array would not be suitable as a VHDL keyword. If you think it is, you need to suggest it at https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Why are there only 3 languages for FPGA development?
For those who would like to see additional features / simplifications in VHDL, the working group accepts issues at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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A new suggested keyword register_array for VHDL
Reddit is not really a great place to suggest language modifications. The vhdl committee have a gitlab issues page where new language ideas can be submitted.. https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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sphinx-vhdl: Automatic generation of documentation from VHDL
See: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
- Include I/O ports using parameter
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Active Busy VHDL Discussion Groups?
You too can contribute to the next revision of VHDL at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Why is verilog more popular?
The IEEE WG welcomes new participants - especially people like yourself who have some experience. Got a good idea, you can interact with the VHDL WG community here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Signed Type vs Integer Type
If you want to get involved with language updates, we now use git issues. See here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
- VHDL Standards and You ...
RedPitaya-FPGA
Posts with mentions or reviews of RedPitaya-FPGA.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-02-02.
-
What would be your go-to solution for configurable number of entity's output signals? (VHDL)
You could use this implementation as a reference: https://github.com/RedPitaya/RedPitaya-FPGA/blob/master/rtl/asg.sv It is similar to what you are trying to make.
What are some alternatives?
When comparing VHDL-Issues and RedPitaya-FPGA you can also consider the following projects:
sphinx-vhdl
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework