HDL_Converter
A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches. (by m47812)
Symbolica
Symbolica's open-source symbolic execution engine. [Moved to: https://github.com/Symbolica/Symbolica] (by SymbolicaDev)
HDL_Converter | Symbolica | |
---|---|---|
1 | 2 | |
5 | 39 | |
- | - | |
0.0 | 8.3 | |
about 2 years ago | over 2 years ago | |
C# | C# | |
GNU Affero General Public License v3.0 | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
HDL_Converter
Posts with mentions or reviews of HDL_Converter.
We have used some of these posts to build our list of alternatives
and similar projects.
Symbolica
Posts with mentions or reviews of Symbolica.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-10-26.
What are some alternatives?
When comparing HDL_Converter and Symbolica you can also consider the following projects:
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
alive2 - Automatic verification of LLVM optimizations
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
Symbolica - Symbolica's open-source symbolic execution engine.
uLab-system-builder - This program generates project settings (such as pin assignments) and basic Verilog code for the μLab Kiwi FPGA development board