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Mentions
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Stars | Project | Description |
|---|---|---|---|
| 26 | 2,232 | VHDL 2008/93/87 simulator | |
| 3 | 1,479 | Official repository of the AWS EC2 FPGA Hardware and Software Development Kit | |
| 77 | 1,437 | :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | |
| 1 | 1,239 | A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards. | |
| 10 | 688 | VUnit is a unit testing framework for VHDL/SystemVerilog | |
| 29 | 652 | GameCube Digital AV converter | |
| 5 | 630 | GPL v3 2D/3D graphics engine in verilog | |
| 25 | 392 | SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network. | |
| 4 | 371 | SNES for the Analogue Pocket | |
| 2 | 363 | bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem | |
| 2 | 357 | Open Source 4k CSI-2 Rx core for Xilinx FPGAs | |
| 1 | 351 | Implementation of a Tensor Processing Unit for embedded systems and the IoT. | |
| 3 | 335 | Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer | |
| 6 | 328 | UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/ | |
| 2 | 315 | A Forth CPU and System on a Chip, based on the J1, written in VHDL | |
| 8 | 301 | ||
| 1 | 295 | Turning .NET software into FPGA hardware for faster execution and lower power usage. | |
| 6 | 292 | VHDL synthesis (based on ghdl) | |
| 1 | 288 | A huge VHDL library for FPGA development | |
| 3 | 274 | An implementation of DisplayPort protocol for FPGAs |
Popular VHDL Topics
Latest Mentions
Latest mentioned VHDL repos
| Stars | Project |
|---|---|
| 8 | FCDRAM |
| 66 | FPGA-radio |
| 1,479 | aws-fpga |
| 111 | bit-serial |
| 392 | satcat5 |
| 13 | vextproj |
| 274 | FPGA_DisplayPort |
| 630 | gplgpu |
| 6 | OcPoC_Mini_Zynq_Files |
| 36 | microCore |
| 106 | Rudi-RV32I |
| 1 | test_hvhdl_ethernet |
| 652 | gcvideo |
| 330 | Mister64 |
| 156 | neoTRNG |
| 28 | RowPress |
| 11 | VHDL-Nexus |
| 31 | Atari2600_MiSTer |
| 24 | aes-over-pcie |
| 53 | neorv32-setups |
Latest Discoveries
Latest discovered VHDL repos
| Stars | Project |
|---|---|
| 8 | FCDRAM |
| 66 | FPGA-radio |
| 111 | bit-serial |
| 13 | vextproj |
| 6 | OcPoC_Mini_Zynq_Files |
| 36 | microCore |
| 1 | test_hvhdl_ethernet |
| 330 | Mister64 |
| 28 | RowPress |
| 11 | VHDL-Nexus |
| 31 | Atari2600_MiSTer |
| 24 | aes-over-pcie |
| 2 | Level-Shifter |
| 4 | VHDL-Learning |
| 10 | ira |
| 24 | USB-Injection |
| 9 | Arcade-TaitoSystemSJ_MiSTer |
| 8 | Arcade_Galaga |
| 0 | DSP |
| 8 | NeoGeo_FPGA |
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FPGA for Deep Learning: Survey and Future Directions
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Layout of Rust's u128 and i128 changed
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Finding the Right "Brain" and Software for Civilian Drone. Part 2
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Show HN: SatCat5, the open-source FPGA Ethernet switch