Top 3 VHDL Asic Projects

vunit

10 688 8.2 VHDL

VUnit is a unit testing framework for VHDL/SystemVerilog
surf

1 288 8.7 VHDL

A huge VHDL library for FPGA development (by slaclab)
InfluxDB

www.influxdata.com featured

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
neoTRNG

10 156 7.3 VHDL

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Project mention: A really tiny and platform-independent true random number generator for FPGAs and ASICs | /r/cryptography | 2023-11-06

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

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Converting VHDL to Verilog using GHDL

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Converting VHDL to Verilog using GHDL

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Code Checking for VHDL

2 projects | /r/FPGA | 11 May 2022

Index

What are some of the best open-source Asic projects in VHDL? This list will help you:

	Project	Stars
1	vunit	688
2	surf	288
3	neoTRNG	156

VHDL Asic

Top 3 VHDL Asic Projects

vunit

surf

InfluxDB

neoTRNG

VHDL Asic related posts

Converting VHDL to Verilog using GHDL

Converting VHDL to Verilog using GHDL

Code Checking for VHDL

Index