Converting VHDL to Verilog using GHDL

• ghdl

  26 2,257 9.8 VHDL

  VHDL 2008/93/87 simulator

  

Maybe you could try to minimize your example to a MWE (minimum working example that demonstrates the issue) and then do a bug report against GHDL at https://github.com/ghdl/ghdl/issues

• InfluxDB

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• neorv32-verilog

  5 45 8.0 Verilog

  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

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