VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Why do you think that https://github.com/YosysHQ/oss-cad-suite-build is a good alternative to vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Why do you think that https://github.com/YosysHQ/oss-cad-suite-build is a good alternative to vscode-terosHDL