A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
Why do you think that https://github.com/CompuSAR/simple_ddr_ctrl is a good alternative to ddr3-controller
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
Why do you think that https://github.com/CompuSAR/simple_ddr_ctrl is a good alternative to ddr3-controller