A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.
Why do you think that https://github.com/OmriRaz/uLab-system-builder is a good alternative to HDL_Converter