Python/C/RTL cosimulation with Xilinx's xsim simulator
Why do you think that https://github.com/alexforencich/verilog-ethernet is a good alternative to pyxsi
Python/C/RTL cosimulation with Xilinx's xsim simulator
Why do you think that https://github.com/alexforencich/verilog-ethernet is a good alternative to pyxsi