A simple three-stage RISC-V CPU
Why do you think that https://github.com/chipsalliance/Cores-VeeR-EH1 is a good alternative to simple-riscv
A simple three-stage RISC-V CPU
Why do you think that https://github.com/chipsalliance/Cores-VeeR-EH1 is a good alternative to simple-riscv