A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
Why do you think that https://github.com/stnolting/neorv32 is a good alternative to RISCV
A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
Why do you think that https://github.com/stnolting/neorv32 is a good alternative to RISCV