This project will compile verilog (a hardware description language) into factorio blueprints.
Why do you think that https://github.com/Halke1986/factorio-riscv is a good alternative to verilog2factorio
This project will compile verilog (a hardware description language) into factorio blueprints.
Why do you think that https://github.com/Halke1986/factorio-riscv is a good alternative to verilog2factorio