A rudimental RISCV CPU supporting RV32I instructions, in VHDL
Why do you think that https://github.com/eugene-tarassov/vivado-risc-v is a good alternative to Rudi-RV32I
A rudimental RISCV CPU supporting RV32I instructions, in VHDL
Why do you think that https://github.com/eugene-tarassov/vivado-risc-v is a good alternative to Rudi-RV32I