Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
Why do you think that https://github.com/chipsalliance/Surelog is a good alternative to hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
Why do you think that https://github.com/chipsalliance/Surelog is a good alternative to hdlConvertor