UART to AXI Stream interface written in VHDL
Why do you think that https://github.com/jakubcabal/cyc1000-rsu is a good alternative to vhdl-axis-uart
UART to AXI Stream interface written in VHDL
Why do you think that https://github.com/jakubcabal/cyc1000-rsu is a good alternative to vhdl-axis-uart