Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
Why do you think that https://github.com/jputcu/serialport is a good alternative to verismith
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
Why do you think that https://github.com/jputcu/serialport is a good alternative to verismith