RISC-V based Single Board Computers are getting there

This page summarizes the projects mentioned and recommended in the original post on news.ycombinator.com

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  • archriscv-packages

    Modified Arch Linux packages for archriscv

  • Glad to hear that you'd like to try! You can report issues at https://github.com/felixonmars/archriscv-packages

    ldc refers to the LLVM-based D Compiler: https://github.com/ldc-developers/ldc

  • byte-unixbench

    Automatically exported from code.google.com/p/byte-unixbench

  • Some of the most interesting benchmarks here:

    Dhrystone 2: 253.2 on the Mango Pi MQ Pro, 202 on the Raspberry Pi Zero. I don't know what this number is; presumably it's not Dhrystone MIPS (VAX MIPS), because that should be closer to 1000 for both chips, and it can't possibly be Dhrystones per second, because a VAX MIPS is 1757 Dhrystones per second, so they ought to be about 1.8 million Dhrystones per second. Reading https://github.com/kdlucas/byte-unixbench/blob/master/UnixBe... leaves me no wiser.

    File Copy 1024: 124.4 on the MQ Pro, 86 on the Raspberry Pi Zero. The UnixBench README says this is measured in the number of characters that can be written, read, and copied in 10 seconds; if this were correct it would mean the MQ Pro were copying 12.4 bytes per second and the Raspberry Pi Zero W was copying 8.6 bytes per second. It seems inescapable that Bret's results are incorrect by several orders of magnitude here.

    C copy backwards: 1197.4 MB/s (not MiB/s as I previously read incorrectly) on the MQ Pro, 157.2 on the Zero W. Something went wrong here.

    Standard memcpy: 1200.9 MB/s on the MQ Pro, 424.8 on the Zero W.

    Standard memset: 2650.6 MB/s on the MQ Pro, 1699.9 on the Zero W. This seems surprisingly slow; you'd think an 8x-unrolled loop of SD instructions on a 1GHz RISC-V would memset about 5 gigabytes per second, if it got one instruction per clock, which it normally ought to. The XuanTie C906 core in the AllWinner D1 C906 is 64-bit, which is potentially an advantage for this; the analogous code for ARM6 can only write 32 bits per instruction. (The ARM has an STM instruction that stores multiple registers, but it doesn't actually run faster.) I'm not sure what happened to the extra factor of 2 in performance. Similar remarks apply to the memcpy results above.

    Amazon Basics 64GB MicroSD card: MQ Pro reads sequentially at 11.48 MB/s, writes sequentially at 10.77 MB/s; Zero W reads sequentially at 21.36 MB/s, writes sequentially at 19.6 MB/s. (I'm ignoring the random reads and writes because he doesn't specify the read and write size, yet he gives the results in MB/s instead of IOPS.) Note that these are six orders of magnitude faster than the 12.4 and 8.6 bytes per second given earlier.

    Unfortunately Weber doesn't link to the benchmark code or document his compilation and execution environment. Presumably the memset and memcpy results are largely measuring the performance of the libc functions, for example, so reproducing them would require knowing if he's using glibc, musl, or a C library he wrote himself.

    Mostly I feel like these benchmarking results are not well enough specified to be useful, which is a shame. I'd like to be able to use this kind of benchmark to predict the performance of a system within a factor of 5 or so, but these results are too irreproducible for that.

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  • ldc

    The LLVM-based D Compiler.

  • Glad to hear that you'd like to try! You can report issues at https://github.com/felixonmars/archriscv-packages

    ldc refers to the LLVM-based D Compiler: https://github.com/ldc-developers/ldc

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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