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They are here https://github.com/AdiuvoEngineering/VHDL_Coding_Rules
You may be interested in our style guides at lowRISC. We publish our styles guides for SystemVerilog, split into synthesizable and DV guides here: https://github.com/lowRISC/style-guides
NOTE:
The number of mentions on this list indicates mentions on common posts plus user suggested alternatives.
Hence, a higher number means a more popular project.