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After this follow up on the Oberon System 3, with its Gadgets component model, and a mix of JIT/AOT compilers,
"The Oberon companion - a guide to using and programming Oberon System 3"
https://www.semanticscholar.org/paper/The-Oberon-companion-a...
You can access the source code from Rochus fork,
https://github.com/rochus-keller/OberonSystem3
Or the Active Oberon evolution, although not directly done by Niklaus Wirth,
https://gitlab.inf.ethz.ch/felixf/oberon
Screenshots and OS Manual,
https://gitlab.inf.ethz.ch/felixf/oberon/-/blob/main/ocp/Doc...
Or Component Pascal and Blackbox IDE, created by a startup out of ETHZ
https://blackboxframework.org/index.php
I re-typeset the text in TeX and have a nicer looking PDF for those that care: https://github.com/guidoism/tex-oberon
The Active Oberon evolution started with the Active Object System (AOS) with the Bluebottle window manager; the source code of the last "Current" version can be accessed e.g. here: https://github.com/OberonSystem3/AOS_Bluebottle_Sources. If you want to study the source code, you can use this tool: https://github.com/Rochus-Keller/ActiveOberon.
The Active Oberon evolution started with the Active Object System (AOS) with the Bluebottle window manager; the source code of the last "Current" version can be accessed e.g. here: https://github.com/OberonSystem3/AOS_Bluebottle_Sources. If you want to study the source code, you can use this tool: https://github.com/Rochus-Keller/ActiveOberon.
this sort of exists at https://github.com/cksystemsteaching/selfie
> Selfie is a self-contained 64-bit, 12KLOC C implementation of: (...) a tiny (...) subset of C called C Star (C) (...) to a tiny (...) subset of RISC-V called RISC-U[;] a[n] (...) emulator (...) that executes RISC-U code[;] (...) a (...) hypervisor (...) that provides RISC-U virtual machines*
so they have an instruction set architecture, a compiler, and an operating system, though it's much simpler than xv6. because the instruction set is a subset of risc-v you can run its code on actual risc-v hardware (or qemu-system-riscv), but presumably you could also design risc-u hardware in verilog that was simpler than a full implementation of rv64i with whatever extensions the hypervisor needs
Related posts
- A tiny hand crafted CPU emulator, C compiler, and Operating System
- Selfie: An educational platform for teaching systems engineering
- Selfie: An educational platform for teaching systems engineering
- An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosting RISC-V hypervisor.
- An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosting RISC-V hypervisor.