Nexys A7 and Vivado's Clocking Wizard

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA

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  • digilent-xdc

    A collection of Master XDC files for Digilent FPGA and Zynq boards.

    • I'm using the Nexys A7 constraint file provided by Digilent, which describes the main clock as follows: set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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