pin-uart
clash-spaceinvaders
pin-uart | clash-spaceinvaders | |
---|---|---|
2 | 1 | |
24 | 46 | |
- | - | |
2.9 | 0.0 | |
about 1 year ago | over 1 year ago | |
Tcl | Tcl | |
- | MIT License |
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pin-uart
- Pin UART FPGA board-level debugging and reverse-engineering tool
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Reverse engineering unsocumented FPGA board?
This concept can be handy, https://github.com/alexforencich/pin-uart
clash-spaceinvaders
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Linear types for circuit design in Haskell/Clash
The largest repo of public Clash code is probably https://github.com/gergoerdi/clash-spaceinvaders What’s nice about it in my view is that it takes a really Haskell-centric approach (as apposed to a write-verilog-in-Haskell approach)
What are some alternatives?
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
VELDT-getting-started - Where Lions Roam: Haskell & Hardware on VELDT
red-pitaya-notes - Notes on the Red Pitaya Open Source Instrument
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
panologic - PanoLogic Zero Client G1 reverse engineering info
kansas-lava-cores - IP Cores written in Kansas Lava
make_for_vivado - experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
ICFP2020_Bluespec_Tutorial - Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
color3 - Information about eeColor Color3 HDMI FPGA board
panologic-g2 - Pano Logic G2 Reverse Engineering Project