eater-sap-1-improvements VS bespokeasm

When I figure out why the "voice" is unintelligible, I will be certainly posting all the details and making a video as I have done with my prior projects for this computer. Subscribe to my YouTube or follow my GitHub repository to get alerts.

The details of my design evolution from the Eater SAP-1 to what you see here are documented at my GitHub repository. You can also watch video overviews if each improvement project at my YouTube channel, the I haven’t yet made the video for the ALU that’s enabling multiplication and division through bit shifting. That’s only at my GitHub at the moment.

Ha ... yeah, it was overkill, but the 32K was just sitting there unused. If you check out my code for the prime number calculation, you'll see the stack is well used. However, I haven't cracked the 256 byte depth yet.

I am using the ATF22V10C in my build. Works great. I’ve made some notes on programming them here: https://github.com/michaelkamprath/eater-sap-1-improvements/tree/advanced-alu/advanced-alu/pld-files

I’ve done a number of upgrades myself. They are documented here: https://github.com/michaelkamprath/eater-sap-1-improvements

Here's the write button. https://i.imgur.com/N3WgqR9.jpg I've inverted it from a pull-up switch to GND, to a pull-down switch to VCC, using Michael Kamprath's improvement recommendations found at https://github.com/michaelkamprath/eater-sap-1-improvements/tree/main/improving-reliability-of-ram-module

This iteration on the CPU focused on implementing a 8-bit instruction register. However, doing this required me to rethink many parts of the computer, notably the memory map and the control logic. Details on what I accomplished in this project can be found in my GitHub repository: https://github.com/michaelkamprath/eater-sap-1-improvements/tree/main/instruction-register-8-bit

If you want to read up on what I am doing here before I create a video on it, I have documented everything here (though there are a few bits I still need to document).

You can check out the current state of my design on my ram-upgrade branch in my GitHub repository. It's still a work in progress, so don't yet expect the same level of documentation or completeness my other modules have.

Cool. If you want to upgrade from your excel/python assembler, you should be able to create a custom ISA with my assembler, BespokeASM: https://github.com/michaelkamprath/bespokeasm

Of course, I did what I do and I added support for this computer in my BespokeASM customizable assembler. This allowed me to write some larger projects than slu4's "minimal assembler" easily enabled. And with that, I ported my 32-bit primes calculation code to the slu4 Minimal CPU. What I found fascinating is that this code ran about the same speed (the PUTEY-1 is a small bit slower) in terms of how long it takes to find a prime value as the code runs on my PUTEY-1 breadboard TTL running at about one fourth the clock speed (480 KHz vs 1.8432 MHz). I attribute that to the more sophisticated ALU I built in my TTL CPU that does bit shifting (left and right) and value comparisons directly in hardware. Of course, I understand that the Minimal CPU's whole goal is to be minimal, I just still found this comparison interesting.

I took have worked on and developed a compiler that is actually read to encode stack operation including indirect value referencing with an address offset to get the mov a, [sp+2] type instructions. You can check it out here: BespokeASM. I have some more development to do with this assembler, notably around macros, includes, and other assembler directives, but the basics for the various addressing modes are in there and the ability to define your instruction set through configuration.