clash-spaceinvaders
pin-uart
| clash-spaceinvaders | pin-uart | |
|---|---|---|
| 1 | 2 | |
| 46 | 24 | |
| - | - | |
| 0.0 | 2.9 | |
| over 1 year ago | about 1 year ago | |
| Tcl | Tcl | |
| MIT License | - |
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clash-spaceinvaders
-
Linear types for circuit design in Haskell/Clash
The largest repo of public Clash code is probably https://github.com/gergoerdi/clash-spaceinvaders What’s nice about it in my view is that it takes a really Haskell-centric approach (as apposed to a write-verilog-in-Haskell approach)
pin-uart
- Pin UART FPGA board-level debugging and reverse-engineering tool
-
Reverse engineering unsocumented FPGA board?
This concept can be handy, https://github.com/alexforencich/pin-uart
What are some alternatives?
VELDT-getting-started - Where Lions Roam: Haskell & Hardware on VELDT
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
red-pitaya-notes - Notes on the Red Pitaya Open Source Instrument
kansas-lava-cores - IP Cores written in Kansas Lava
panologic - PanoLogic Zero Client G1 reverse engineering info
ICFP2020_Bluespec_Tutorial - Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
make_for_vivado - experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
color3 - Information about eeColor Color3 HDMI FPGA board
panologic-g2 - Pano Logic G2 Reverse Engineering Project