A64FX VS PurefunctionPipelineDataflow

This is their main repo https://github.com/fujitsu/A64FX

You should check the architecture manual https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Microarchitecture_Manual_en_1.0.pdf

> I'm somewhat curmudgeonly w.r.t. SVE, insisting that while the sole system in existence is a HPC machine from Fujitsu, that for practical purposes it doesn't really exist and isn't worth learning. I will likely revise this opinion when ARM vendors decide to ship something (likely soon, by most roadmaps).

Fair enough. I have high hopes for SVE, though. The first-faulting memory ops and predicate bisection features look like a vectorization godsend.

> There's only so much space in my brain.

I'm still going to attempt a nerd-sniping with the published architecture manual. Fujitsu includes a detailed pipeline description including instruction latencies. Granted its just one part, and its an HPC-focused part at that. But its not every day that this level of detail gets published in the ARM world.

https://github.com/fujitsu/A64FX/tree/master/doc

> I was irate to discover that you can't do logic ops on 8b/16b lanes with masking; as usual the 32b/64b mafia strike again.

SVE is blessedly uniform in this regard.

> It would be nice if the explicit mask operations were cheaper. Unfortunately, they crowd out SIMD operations.

This goes both ways, though. A64FX has two vector execution pipelines and one dedicated predicate execution pipeline. Since the vector pipelines cannot execute predicate ops, I expect it is not difficult to construct cases where code gets starved for predicate execution resources.

The A64fx also has hardware synchronization barriers to synchronize cores, which is a pretty GPU-like thing (at least it is very common on GPUs, and rare on CPUs).

https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Speci...

Implement relational data model and programming based on hash-map (NoSQL)

The Math-based Grand Unified Programming Theory: The Pure Function Pipeline Data Flow with Principle-based Warehouse/Workshop Model

I criticized "AMD Infinity Fabric Architecture" at the end of my article "Prediction: Intel will use "RISC-V plus x86 compatibility layer" or "RISC-V plus x86 heterogeneous computing architecture" to develop a new generation of "warehouse/workshop model" CPU".

What's more, you're being somewhat liberal with your "invention" dates here anyway. I'm sure you realize that anyone can review the commit history to see when content was added to the repo. As of Nov 2020, the day Apple announced a fully operational and tested, ready-to-ship silicon package the repo was a just series of bullet points listing out well-known concepts of functional programming sprinkled with some religious analogies and inspirational quotes. The farther you go back in the repo commit history, the less content is there.