VHDL asic-design

Open-source VHDL projects categorized as asic-design
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Topics: Cryptography Random Asic Fpga Vhdl
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VHDL asic-design Projects

asic-design

  • neoTRNG

    🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

    • Project mention: A really tiny and platform-independent true random number generator for FPGAs and ASICs | /r/cryptography | 2023-11-06

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

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1 neoTRNG 157

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Power Real-Time Data Analytics at Scale
Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
www.influxdata.com