Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality. Learn more →
Riscv-isa-manual Alternatives
Similar projects and alternatives to riscv-isa-manual
-
InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
-
SaaSHub
SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives
-
picocli
Picocli is a modern framework for building powerful, user-friendly, GraalVM-enabled command line apps with ease. It supports colors, autocompletion, subcommands, and more. In 1 source file so apps can include as source & avoid adding a dependency. Written in Java, usable from Groovy, Kotlin, Scala, etc.
-
SaaSHub
SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives
riscv-isa-manual reviews and mentions
-
The Improved RISC-V Specification (latest WIP draft)
https://github.com/riscv/riscv-isa-manual/releases
Regarding the recent "How to improve the RISC-V specification" post [0], I just wanted to point out, that the latest draft manual is already a great improvement. (see link above)
It includes a lot of the newly ratified extensions: bitmanip,zicond,vector,vector crypto, ...
And there are a bunch of included SAIL definitions for bitmanip and zicond, but other instructions are still missing the SAIL code. Most notably, the SAIL definitions from the RV32I/RV64I base isa are also missing.
I asked for the further SAIL integration plans here: https://github.com/riscv/riscv-isa-manual/issues/1369
Here is an example SAIL snippet from cpopw:
let bitcount = 0;
-
How to improve the RISC-V specification
I encourage you to look at the newest isa manual draft on github: https://github.com/riscv/riscv-isa-manual/releases
It includes the more recently extensions, and e.g. the bitmanip instructions all have associated pseudo code.
Here is e.g. the code for cpopw:
let bitcount = 0;
- Need help with designing a basic RISC V processor?
-
The legend of “x86 CPUs decode instructions into RISC form internally”
I tried searching the spec [1] for "overflow" and here is what it says at page 17:
> We did not include special instruction-set support for overflow checks on integer arithmetic operations in the base instruction set, as many overflow checks can be cheaply implemented using RISC-V branches.
> For general signed addition, three additional instructions after the addition are required
Is this "cheap", replacing 1 instruction with four? According to some old mainframe era research (cannot find link now), addition is the most often used instruction and they suggest that we should replace each one with four?
Their "rationale" is not rational at all. It doesn't make sense.
Overflow check should be free (no additional instructions required), otherwise we will see the same story we have seen for last 50 years: compiler writers do not want to implement checks because they are expensive; language designers do not want to use proper arithmetic because it is expensive. As a result, there will be errors and vulnerabilities. A vicious circle.
[1] https://github.com/riscv/riscv-isa-manual/releases/download/...
- 64-bit Arm ∩ 64-bit RISC V
- Beginner question: F extension
-
Riscv Ghidra Instruction Manual
Why not use the actual release PDF instead from their github? https://github.com/riscv/riscv-isa-manual
-
How would I go about designing an 8-bit RISC-V CPU? Is it possible?
https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf Part 2
-
Have to convert a C language code into RISC-V MIPS
If you don't want to cheat then read the RISC-V ISA manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
-
How does a computer understand machine language?
Yeah you are on the right track. Processors are designed on top of an Instruction Set Architecture (ISA). For an example you can look on top of the RISC-V specifications:https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf (possible PDF download)
-
A note from our sponsor - InfluxDB
www.influxdata.com | 17 May 2024
Stats
riscv/riscv-isa-manual is an open source project licensed under Creative Commons Attribution 4.0 which is not an OSI approved license.
The primary programming language of riscv-isa-manual is TeX.
Popular Comparisons
- riscv-isa-manual VS riscv-elf-psabi-doc
- riscv-isa-manual VS riscv-emulator-docker-image
- riscv-isa-manual VS amaranth
- riscv-isa-manual VS riscv-v-spec
- riscv-isa-manual VS vroom
- riscv-isa-manual VS open-source-cs
- riscv-isa-manual VS ibex
- riscv-isa-manual VS riscv-bitmanip
- riscv-isa-manual VS rocket-chip
- riscv-isa-manual VS branch-hinting
Sponsored