Any better options than Sigasi?

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA
Vhdl language-server modelsim Xilinx vhdl-parser

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  • hdl_checker

    Repurposing existing HDL tools to help writing better code

    • I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker

  • rust_hdl

    • I'm using emacs + rust_hdl as LSP and it provides me live-error-checking for VHDL designs. You should be able to use rust_hdl with any text editor of your choice as long as it supports LSP.

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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