xv6-riscv
riscv-gnu-toolchain
xv6-riscv | riscv-gnu-toolchain | |
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17 | 35 | |
6,309 | 3,200 | |
6.8% | 4.6% | |
0.0 | 8.2 | |
12 days ago | 12 days ago | |
C | C | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
xv6-riscv
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The rxv64 Operating System: MIT's xv6, in Rust, for SMP x86_64 machines
okay, fair. i only got misled by the title of the post, which claims all-rust xv6 port.
now that we cleared the userland part, here’s what I’m contemplating on the kernel side. i can’t think of anything simpler and more staple than this, so:
https://github.com/dancrossnyc/rxv64/blob/main/kernel/src/ua...
https://github.com/mit-pdos/xv6-riscv/blob/riscv/kernel/uart...
honestly - i don’t feel at ease to tell which driver code is more instructional, which is easier to read, which is better documented, which is better covered with tests, which has more unsafety built into it (explicit or otherwise), what size are the object files, and what is easier to cross-compile and run on the designated target from, say, one of now-ubiquitous apple silicon devices.
lest we forget that the whole point of it is “pedagogical”, i.e. to learn something about how a modern OS can be organized, and how computer generally works.
and i’m just not sure.
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Xv6: A modern, x86 reimplementation of 6th Edition Unix
The x86 version of xv6 is no longer updated, the last updates took place about 7 years ago. Current xv6 supports RISC V in qemu, there are also ports to real RISC V devices (Kendryte/Canaan K210, Allwinner D1, StarFive JH7110, some hacked by me) and FPGA implementations ().
https://github.com/mit-pdos/xv6-riscv/ (qemu)
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seeking another faculty member re: xv6
I am no help with recruitment, but simple search revealed "https://github.com/mit-pdos/xv6-riscv", were you aware of this?
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MINIX is an awesome way to learn a wide range of CS concepts
Different repo under same org https://github.com/mit-pdos/xv6-riscv
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Ask HN: Examples of Microkernels?
I'm reading through the MIT xv6 OS handbook and code (here: https://github.com/mit-pdos/xv6-riscv/) and they mention the fact that they created it as a monolithic kernel since most unix systems are monolithic. They then introduce the microkernel concept. Are there microkernel concepts out there (especially code) I can check out? I'm curious to see how userspace processes communicate to kernel processes to execute privileged actions.
- Risc V Assembly and Qemu
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How does multiprocessing on a multivitamin cpu work?
Yeah its from here: https://github.com/mit-pdos/xv6-riscv x86 version here: https://github.com/mit-pdos/xv6-public
- Xv6 for RISC-V
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How do I become an Operating Systems developer?
I would start with working through an OS textbook. Tanenbaum is highly regarded although I worked through OStep and I felt it was very approachable. Also check out wiki.osdev.org. Also, here's a re-inplementation of Unix version 6. I've been meaning to play around with it for a while.
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Can't get xv6 to run on arch linux
NOTE: we have stopped maintaining the x86 version of xv6, and switched our efforts to the RISC-V version (https://github.com/mit-pdos/xv6-riscv.git)
riscv-gnu-toolchain
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Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
> no absurdely and grotesquely massive and complex compilers anywhere
Absence of evidence is not evidence of absence, and anyway there's not even an absence: https://github.com/riscv-collab/riscv-gnu-toolchain https://llvm.org/docs/RISCVUsage.html
> feature creeps on computer language syntax nowhere to be found
At least one of us is very confused, and in case it's me, how do language details matter to RISC-V?
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Help trying to build for riscv64gc-unknown-linux-musl
I then looked at the .cargo/config.toml provided by the guide and saw that it wasn't actually statically compiling the code. After a bit of tinkering and building my own toolchain from here, I ended up with this config.toml file:
- GNU toolchain for RISC-V including GCC
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Building a toolchain suitable for compiling V extension code
b) collabriscv - essentially gcc 12.2 + binutils master/2.40 as per https://github.com/riscv-collab/riscv-gnu-toolchain
- How do i specify vendor name while building the GNU toolchain?
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GCC 13 Adds RISC-V T-Head Vendor Extension Collection
Or would it be better to take what is in https://github.com/riscv-collab/riscv-gnu-toolchain which is gcc 12.2 and start from there?
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How to build toolchain with Zbs extension?
I'm not able to build https://github.com/riscv-collab/riscv-gnu-toolchain.git like this:
What are some alternatives?
xv6-public - xv6 OS
riscv-binutils-gdb - RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
uom - Units of measurement -- type-safe zero-cost dimensional analysis
risc-v-examples - RISC-V examples for GD32V, K210, and QEMU
rrs - Rust RISC-V Simulator
rvv-llvm - This repository is outdated, support for RISC-V is now developed in upstream LLVM
minixfromscratch - Development and compilation setup for the book versions of MINIX (2.0.0 and 3.1.0) on QEMU
buildroot - Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
lambda-calculus - A lambda calculus interpreter that works on desktop and wasm
freedom-tools - Tools for SiFive's Freedom Platform
rxv64 - xv6 OS
riscv-gcc