Vhdl

Open-source projects categorized as Vhdl
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Language: + VHDL + Python + Verilog + C++ + Java + Assembly + Scala + C + Haskell + JavaScript + Ruby
Topics: Fpga Verilog Python Cpu risc-v
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Top 23 Vhdl Open-Source Projects

  • logisim-evolution

    Digital logic design tool and simulator

    • Project mention: Problem with installation | /r/logisim | 2023-07-10

    I have downloaded logisim-evolution from github. While trying to run .msi file, Microsoft Defender blocked it for some reason. I scanned it with some other scanners and everything was fine. I'm not sure if this is safe to install it.

  • VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

    • Project mention: Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide | /r/RISCV | 2023-10-23

    With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

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  • ghdl

    VHDL 2008/93/87 simulator

  • cocotb

    cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

    • Project mention: Designing a Low Latency 10G Ethernet Core | /r/FPGA | 2023-07-04

    The use of cocotb and pyuvm for verification

  • SpinalHDL

    Scala based HDL

    • Project mention: 1800-2023 – IEEE Standard for SystemVerilog | news.ycombinator.com | 2024-04-17

    I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.

    I really like what Zig and C++ are doing with `const`.

    https://ikrima.dev/dev-notes/zig/zig-metaprogramming/

    Have you looked at Spinal?

    https://github.com/SpinalHDL/SpinalHDL

    https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html

  • neorv32

    :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    • Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24

  • clash-ghc

    Haskell to VHDL/Verilog/SystemVerilog compiler

    • Project mention: Clash: A Functional Hardware Description Language | news.ycombinator.com | 2023-12-27

  • WorkOS

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  • fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

    • Project mention: fusesoc VS vextproj - a user suggested alternative | libhunt.com/r/fusesoc | 2024-03-28

  • awesome-hdl

    Hardware Description Languages

  • vunit

    VUnit is a unit testing framework for VHDL/SystemVerilog

  • microwatt

    A tiny Open POWER ISA softcore written in VHDL 2008

    • Project mention: Microwatt: A tiny Open POWER ISA softcore written in VHDL 2008 | /r/patient_hackernews | 2023-10-23

  • edalize

    An abstraction library for interfacing EDA tools

  • riscv_vhdl

    Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

  • PipelineC

    A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

    • Project mention: PipelineC Example: FM Radio Demodulation (FPGA SDR) | news.ycombinator.com | 2024-03-03

    Related: PipelineC: A C-like hardware description language (HDL):

    https://github.com/JulianKemmerer/PipelineC

  • vscode-terosHDL

    VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

  • bladeRF-wiphy

    bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

  • forth-cpu

    A Forth CPU and System on a Chip, based on the J1, written in VHDL

  • rust_hdl

    • Project mention: How to configure vim like an IDE | /r/vim | 2023-06-27

    rust_hdl

  • surf

    A huge VHDL library for FPGA development (by slaclab)

  • rggen

    Code generation tool for control and status registers

  • hdlConvertor

    Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

  • potato

    A simple RISC-V processor for use in FPGA designs. (by skordal)

  • Degate

    A modern and open-source cross-platform software for chips reverse engineering.

    • Project mention: Semi-automatic VLSI reverse engineering of digital logic in chips | news.ycombinator.com | 2024-02-02

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Vhdl related posts

Index

What are some of the best open-source Vhdl projects? This list will help you:

Project Stars
1 logisim-evolution 4,307
2 VexRiscv 2,252
3 ghdl 2,206
4 cocotb 1,599
5 SpinalHDL 1,518
6 neorv32 1,415
7 clash-ghc 1,372
8 fusesoc 1,115
9 awesome-hdl 871
10 vunit 681
11 microwatt 643
12 edalize 590
13 riscv_vhdl 578
14 PipelineC 541
15 vscode-terosHDL 490
16 bladeRF-wiphy 363
17 forth-cpu 315
18 rust_hdl 298
19 surf 284
20 rggen 277
21 hdlConvertor 264
22 potato 245
23 Degate 229

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