Top 21 Verilator Open-Source Projects

• verilator

  11 2,083 9.8 C++

  Verilator open-source SystemVerilog simulator and lint system

  

Project mention: What's new for RISC-V in LLVM 17 | news.ycombinator.com | 2023-10-11

You may want to check out Verilator:

https://verilator.org/

• zipcpu

  13 1,190 6.3 Verilog

  A small, light weight, RISC CPU soft core

• InfluxDB

  www.influxdata.com sponsored

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• riscv

  2 1,040 1.8 Verilog

  RISC-V CPU Core (RV32IM)

Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

• Cores-VeeR-EH1

  8 773 0.0 SystemVerilog

  VeeR EH1 core

  

• biriscv

  6 749 0.0 Verilog

  32-bit Superscalar RISC-V CPU

Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21

• edalize

  4 590 7.3 Python

  An abstraction library for interfacing EDA tools

• wbuart32

  4 250 4.6 Verilog

  A simple, basic, formally verified UART controller

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• WorkOS

  workos.com sponsored

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• Cores-VeeR-EL2

  1 222 9.2 SystemVerilog

  VeeR EL2 Core

  

• dblclockfft

  1 205 2.5 C++

  A configurable C++ generator of pipelined Verilog FFT cores

• FakePGA

  1 152 1.8 CMake

  Simulating Verilog designs on a microcontroller

• vgasim

  11 147 1.2 Verilog

  A Video display simulator

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• sdspi

  4 132 7.5 Verilog

  SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• openarty

  6 116 0.0 Verilog

  An Open Source configuration of the Arty platform

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

• dpll

  2 87 2.8 Verilog

  A collection of phase locked loop (PLL) related projects

• wbscope

  1 70 3.7 Verilog

  A wishbone controlled scope for FPGA's

• interpolation

  1 48 3.2 Verilog

  Digital Interpolation Techniques Applied to Digital Signal Processing

• zbasic

  4 40 0.0 Verilog

  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

• eda_tools

  2 34 2.0 Dockerfile

  A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.

• dbgbus

  5 31 3.9 Verilog

  A collection of debugging busses developed and presented at zipcpu.com

• wbicapetwo

  2 8 0.0 Verilog

  Wishbone to ICAPE interface conversion

• verilog_template

  1 0 2.6 Makefile

  A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

• SaaSHub

  www.saashub.com sponsored

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Verilator related posts

• What's new for RISC-V in LLVM 17
  2 projects | news.ycombinator.com | 11 Oct 2023
• Ultraembedded RISCV Module
  1 project | /r/RISCV | 4 Aug 2023
• C++ Verification Testbench Best-Practice Resources?
  7 projects | /r/FPGA | 11 Jun 2023
• How to run & simulate system verilog files on VScode?
  1 project | /r/chipdesign | 11 Feb 2023
• Choosing a Verification Methodology
  1 project | /r/FPGA | 7 Nov 2022
• Five legally free FPGA books (plus one about Machine Learning)
  1 project | /r/FPGA | 6 Sep 2022
• PLL simulation in Vivado
  1 project | /r/FPGA | 10 Aug 2022
• A note from our sponsor - WorkOS
  workos.com | 25 Apr 2024

  The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning. Learn more →

Index

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