Top 10 system-on-chip Open-Source Projects

litex

29 2,672 9.7 C

Build your hardware, easily!

Project mention: FPGA Dev Boards for $150 or Less | news.ycombinator.com | 2023-11-06

https://github.com/enjoy-digital/litex
they have tutorials, you can get compatible boards for around $20

neorv32

77 1,415 9.9 C

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24

InfluxDB

www.influxdata.com sponsored

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
openlane

12 1,174 8.6 Python

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
esp

1 295 7.6 C

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
antikernel

2 110 0.0 Verilog

The Antikernel operating system project
Introduction-to-SoC-Design-Education-Kit

1 78 4.8 HTML

Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
ESP32_Thing

1 72 0.0

Development platform for the Espressif ESP32 WiFi/Microcontroller SoC
WorkOS

workos.com sponsored

The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
spu32

1 60 0.0 C

Small Processing Unit 32: A compact RV32I CPU written in Verilog
FazyRV

1 56 7.4 SystemVerilog

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Project mention: FazyRV – A Scalable RISC-V Core | news.ycombinator.com | 2024-03-01

zbasic

4 39 0.0 Verilog

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).