Riscv

Open-source projects categorized as Riscv | Edit details
Related topics: #risc-v #Rtl #Fpga #Cpu #Rv32i

Top 23 Riscv Open-Source Projects

  • GitHub repo capstone

    Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings. (by aquynh)

    Project mention: Capstone Disassembler Framework | news.ycombinator.com | 2021-03-05
  • GitHub repo rocket-chip

    Rocket Chip Generator

    Project mention: FPGA for RISC-V Processor | reddit.com/r/FPGA | 2021-10-01
  • Scout APM

    Scout APM: A developer's best friend. Try free for 14-days. Scout APM uses tracing logic that ties bottlenecks to source code so you know the exact line of code causing performance issues and can get back to building a great product faster.

  • GitHub repo cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    Project mention: What is Purism's roadmap for open-source hardware/schematics? | reddit.com/r/Purism | 2021-09-29

    When the OpenHW Group was created in 2019, I had some hope that Alibaba or NXP (who are in the OpenHW Group) would release an open hardware RISC-V processor, but it looks like they are not making any public commits to the CVA6 core, so I doubt that we are ever going to see the source code of Alibaba's XT910 or NXP's Chassis RISC-V processor.

  • GitHub repo VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

    Project mention: Intel replaces their NIOS II soft core in their FPGAs with 5x faster NIOS V RISC-V soft core | reddit.com/r/FPGA | 2021-10-04
  • GitHub repo darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

    Project mention: Are there any dual-GBE, PoE-capable SBCs? | reddit.com/r/linuxhardware | 2021-08-20
  • GitHub repo riscv-boom

    SonicBOOM: The Berkeley Out-of-Order Machine

    Project mention: Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'" | reddit.com/r/hardware | 2021-09-08

    We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip

  • GitHub repo chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Project mention: How to use a RISC V core for other purposes? | reddit.com/r/RISCV | 2021-06-08
  • Nanos

    Run Linux Software Faster and Safer than Linux with Unikernels.

  • GitHub repo probe-rs

    A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

    Project mention: We finally released 0.11.0 of probe-rs! 🎉 | reddit.com/r/rust | 2021-06-24

    cargo install --git https://github.com/probe-rs/probe-rs probe-rs-debugger

  • GitHub repo neorv32

    :desktop_computer: A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    Project mention: GitHub - stnolting/neorv32: A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | reddit.com/r/coolgithubprojects | 2021-10-06
  • GitHub repo rars

    RARS -- RISC-V Assembler and Runtime Simulator

    Project mention: RISC V Noobie here | reddit.com/r/RISCV | 2021-04-26
  • GitHub repo cv32e40p

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    Project mention: 2 questions after finishing digital logic | reddit.com/r/ElectricalEngineering | 2021-06-08

    Here is an example of a GitHub repository for a riscv core I found on google: https://github.com/openhwgroup/cv32e40p/tree/master/rtl

  • GitHub repo Cores-SweRV

    SweRV EH1 core

    Project mention: How does philosophy of open source hardware react to "dominant" chip makers? | reddit.com/r/opensource | 2021-09-23
  • GitHub repo scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    Project mention: Mikron MIK32 – Made in Russia 32-bit RISC-V MCU... for about $6 | reddit.com/r/RISCV | 2021-09-10
  • GitHub repo riscv_vhdl

    Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

    Project mention: Wouldn't it be crazy if amd or intel turned around and started making RISK-V based processors to compete with arm? | reddit.com/r/opensource | 2021-09-25

    There is code that describes the processor, the VHDL is also open source. You can get the some similar implementations for older ARM implementations but you may have to pay to use them commercially.

  • GitHub repo rvemu

    RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

    Project mention: RVVM – The RISC-V Virtual Machine | news.ycombinator.com | 2021-07-22

    More emulators lists here:

    https://riscv.org/exchange/software/

    The most popular ones are qemu and spike. There are even a few emulators written in Rust that aren't on the list:

    https://github.com/shady831213/terminus

    https://github.com/d0iasm/rvemu

    I've messed around with Terminus the most.

  • GitHub repo Jupiter

    RISC-V Assembler and Runtime Simulator

    Project mention: RISCV Binary Search Algorithm Error | reddit.com/r/RISCV | 2021-06-24

    Looks like this one: https://github.com/andrescv/Jupiter

  • GitHub repo shecc

    A self-hosting and educational C compiler

    Project mention: Compiler Class | news.ycombinator.com | 2021-02-09

    I'm looking at this one for a CPU design I've been working on. :)

    https://github.com/jserv/shecc

  • GitHub repo lbForth

    Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

    Project mention: Forth on the XMOS CPU? | reddit.com/r/Forth | 2021-06-22

    Probably what I would do is write a minimal forth interpreter in C, and then use that and a few core words to bootstrap the rest of the system. It is a bit more complex than that, but here is the software which does it.https://github.com/larsbrinkhoff/lbForth

  • GitHub repo riscv-mini

    Simple RISC-V 3-stage Pipeline in Chisel

    Project mention: Tips on building a RISC-V processor on FPGA | reddit.com/r/RISCV | 2021-06-15
  • GitHub repo ppci

    A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python

    Project mention: PPCI (Pure Python Compiler Infrastructure) Project | news.ycombinator.com | 2021-10-18
  • GitHub repo RVVM

    The RISC-V Virtual Machine

    Project mention: RVVM – The RISC-V Virtual Machine | news.ycombinator.com | 2021-07-22
  • GitHub repo Cores-SweRV-EL2

    SweRV EL2 Core

    Project mention: Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'" | reddit.com/r/hardware | 2021-09-08

    Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2

  • GitHub repo SaxonSoc

    SoC based on VexRiscv and ICE40 UP5K

    Project mention: How many more years until we have a completely open source RISC-V SOC? | reddit.com/r/RISCV | 2021-05-26

    Most of them might still be missing on the ASIC side, but already exist to some extent on the FPGA side. Litex (https://github.com/enjoy-digital/litex/) is adding support for the USB host (ohci-compatible) developed for Saxon (https://github.com/SpinalHDL/SaxonSoc), in addition to the DRAM, Ethernet (MII, GMII, some RGMII), micro-sd, UART, HDMI framebuffer, ... peripherals that are already supported.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-10-18.

Index

What are some of the best open-source Riscv projects? This list will help you:

Project Stars
1 capstone 5,237
2 rocket-chip 1,993
3 cva6 1,302
4 VexRiscv 1,301
5 darkriscv 1,188
6 riscv-boom 974
7 chipyard 612
8 probe-rs 594
9 neorv32 583
10 rars 525
11 cv32e40p 511
12 Cores-SweRV 480
13 scr1 443
14 riscv_vhdl 385
15 rvemu 355
16 Jupiter 338
17 shecc 318
18 lbForth 318
19 riscv-mini 265
20 ppci 230
21 RVVM 224
22 Cores-SweRV-EL2 108
23 SaxonSoc 93
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