Top 23 Riscv Open-Source Projects
Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings. (by aquynh)Project mention: Capstone Disassembler Framework | news.ycombinator.com | 2021-03-05
Rocket Chip GeneratorProject mention: FPGA for RISC-V Processor | reddit.com/r/FPGA | 2021-10-01
Scout APM: A developer's best friend. Try free for 14-days. Scout APM uses tracing logic that ties bottlenecks to source code so you know the exact line of code causing performance issues and can get back to building a great product faster.
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting LinuxProject mention: What is Purism's roadmap for open-source hardware/schematics? | reddit.com/r/Purism | 2021-09-29
When the OpenHW Group was created in 2019, I had some hope that Alibaba or NXP (who are in the OpenHW Group) would release an open hardware RISC-V processor, but it looks like they are not making any public commits to the CVA6 core, so I doubt that we are ever going to see the source code of Alibaba's XT910 or NXP's Chassis RISC-V processor.
A FPGA friendly 32 bit RISC-V CPU implementationProject mention: Intel replaces their NIOS II soft core in their FPGAs with 5x faster NIOS V RISC-V soft core | reddit.com/r/FPGA | 2021-10-04
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!Project mention: Are there any dual-GBE, PoE-capable SBCs? | reddit.com/r/linuxhardware | 2021-08-20
SonicBOOM: The Berkeley Out-of-Order MachineProject mention: Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'" | reddit.com/r/hardware | 2021-09-08
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and moreProject mention: How to use a RISC V core for other purposes? | reddit.com/r/RISCV | 2021-06-08
Run Linux Software Faster and Safer than Linux with Unikernels.
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate hostProject mention: We finally released 0.11.0 of probe-rs! 🎉 | reddit.com/r/rust | 2021-06-24
cargo install --git https://github.com/probe-rs/probe-rs probe-rs-debugger
:desktop_computer: A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.Project mention: GitHub - stnolting/neorv32: A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | reddit.com/r/coolgithubprojects | 2021-10-06
RARS -- RISC-V Assembler and Runtime SimulatorProject mention: RISC V Noobie here | reddit.com/r/RISCV | 2021-04-26
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-PlatformProject mention: 2 questions after finishing digital logic | reddit.com/r/ElectricalEngineering | 2021-06-08
Here is an example of a GitHub repository for a riscv core I found on google: https://github.com/openhwgroup/cv32e40p/tree/master/rtl
SweRV EH1 coreProject mention: How does philosophy of open source hardware react to "dominant" chip makers? | reddit.com/r/opensource | 2021-09-23
SCR1 is a high-quality open-source RISC-V MCU core in VerilogProject mention: Mikron MIK32 – Made in Russia 32-bit RISC-V MCU... for about $6 | reddit.com/r/RISCV | 2021-09-10
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulatorsProject mention: Wouldn't it be crazy if amd or intel turned around and started making RISK-V based processors to compete with arm? | reddit.com/r/opensource | 2021-09-25
There is code that describes the processor, the VHDL is also open source. You can get the some similar implementations for older ARM implementations but you may have to pay to use them commercially.
RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
More emulators lists here:
The most popular ones are qemu and spike. There are even a few emulators written in Rust that aren't on the list:
I've messed around with Terminus the most.
RISC-V Assembler and Runtime SimulatorProject mention: RISCV Binary Search Algorithm Error | reddit.com/r/RISCV | 2021-06-24
Looks like this one: https://github.com/andrescv/Jupiter
A self-hosting and educational C compiler
Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.Project mention: Forth on the XMOS CPU? | reddit.com/r/Forth | 2021-06-22
Probably what I would do is write a minimal forth interpreter in C, and then use that and a few core words to bootstrap the rest of the system. It is a bit more complex than that, but here is the software which does it.https://github.com/larsbrinkhoff/lbForth
Simple RISC-V 3-stage Pipeline in ChiselProject mention: Tips on building a RISC-V processor on FPGA | reddit.com/r/RISCV | 2021-06-15
A compiler for ARM, X86, MSP430, xtensa and more implemented in pure PythonProject mention: PPCI (Pure Python Compiler Infrastructure) Project | news.ycombinator.com | 2021-10-18
The RISC-V Virtual Machine
SweRV EL2 CoreProject mention: Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'" | reddit.com/r/hardware | 2021-09-08
Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2
SoC based on VexRiscv and ICE40 UP5KProject mention: How many more years until we have a completely open source RISC-V SOC? | reddit.com/r/RISCV | 2021-05-26
Most of them might still be missing on the ASIC side, but already exist to some extent on the FPGA side. Litex (https://github.com/enjoy-digital/litex/) is adding support for the USB host (ohci-compatible) developed for Saxon (https://github.com/SpinalHDL/SaxonSoc), in addition to the DRAM, Ethernet (MII, GMII, some RGMII), micro-sd, UART, HDMI framebuffer, ... peripherals that are already supported.
What are some of the best open-source Riscv projects? This list will help you:
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