Riscv

Open-source projects categorized as Riscv
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Language: + Rust + C + Scala + SystemVerilog + Verilog + C++ + Assembly + Java + Tcl
Topics: risc-v Fpga Rust Arm Cpu
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Top 23 Riscv Open-Source Projects

  • ncnn

    ncnn is a high-performance neural network inference framework optimized for the mobile platform

    • Project mention: AMD Funded a Drop-In CUDA Implementation Built on ROCm: It's Open-Source | news.ycombinator.com | 2024-02-12

    ncnn uses Vulkan for GPU acceleration, I've seen it used in a few projects to get AMD hardware support.

    https://github.com/Tencent/ncnn

  • Unicorn Engine

    Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

    • Project mention: Unicorn: Lightweight multi-platform, multi-architecture CPU emulator framework | news.ycombinator.com | 2023-11-19

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  • capstone

    Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), BPF, Ethereum VM, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

    • Project mention: Rise: Accelerate the Development of Open Source Software for RISC-V | news.ycombinator.com | 2023-05-31

    Maybe then they can help us with the Capstone[1][2] disassembly engine auto-sync (automatic synchronization from the LLVM TableGen files) effort[3]. ARMv7, ARMv8/9, PowerPC are nearly finished, and MIPS in in near-term plans. Nobody stepped in for RISC-V yet.

    [1] http://www.capstone-engine.org/

    [2] https://github.com/capstone-engine/capstone

    [3] https://github.com/capstone-engine/capstone/issues/2015

  • rCore

    Rust version of THU uCore OS. Linux compatible.

  • rocket-chip

    Rocket Chip Generator

  • VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

    • Project mention: Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide | /r/RISCV | 2023-10-23

    With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

  • darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

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  • riscv-boom

    SonicBOOM: The Berkeley Out-of-Order Machine

    • Project mention: Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU | news.ycombinator.com | 2023-12-10

  • probe-rs

    A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

    • Project mention: Where my STM32 Rust compiler? | /r/ProgrammerHumor | 2023-05-11

    Want debugging capabilities with anything with an am st link/jtag/other compatible probe? https://probe.rs/

  • neorv32

    :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    • Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24

  • chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    • Project mention: Chisel: A Modern Hardware Design Language | news.ycombinator.com | 2023-12-27

    It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.

    Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.

    Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.

    [0]: https://github.com/ucb-bar/chipyard

    [1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...

  • octox

    Unix-like OS in Rust inspired by xv6-riscv

    • Project mention: GitHub - o8vm/octox: Unix-like OS in Rust inspired by xv6-riscv | /r/programming | 2023-07-30

  • rars

    RARS -- RISC-V Assembler and Runtime Simulator

  • shecc

    A self-hosting and educational C optimizing compiler

    • Project mention: A self-hosting and educational C optimizing compiler | news.ycombinator.com | 2024-01-07

    Yes, consider the case of shecc. It requires just a handful of C code lines to interpret directives set in the C preprocessor. Unlike relying on existing tools like cpp, as, or ld, shecc stands alone as a minimalist cross-compiler. This design could be particularly beneficial for students delving into the study of compiler construction. See https://github.com/sysprog21/shecc/blob/master/src/lexer.c#L...

  • rustsbi

    RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/standalone.

  • cv32e40p

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  • RVVM

    The RISC-V Virtual Machine

  • scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  • Cores-VeeR-EH1

    VeeR EH1 core

  • vivado-risc-v

    Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  • rvemu

    RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

  • riscv_vhdl

    Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

  • riscv-rust

    RISC-V processor emulator written in Rust+WASM

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Riscv related posts

Index

What are some of the best open-source Riscv projects? This list will help you:

Project Stars
1 ncnn 19,176
2 Unicorn Engine 7,126
3 capstone 7,025
4 rCore 3,326
5 rocket-chip 3,002
6 VexRiscv 2,252
7 darkriscv 1,882
8 riscv-boom 1,593
9 probe-rs 1,474
10 neorv32 1,415
11 chipyard 1,428
12 octox 1,174
13 rars 1,099
14 shecc 1,038
15 rustsbi 924
16 cv32e40p 869
17 RVVM 807
18 scr1 775
19 Cores-VeeR-EH1 773
20 vivado-risc-v 729
21 rvemu 696
22 riscv_vhdl 578
23 riscv-rust 571

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