Top 23 Fpga Open-Source Projects

  • GitHub repo PlatformIO

    PlatformIO is a professional collaborative platform for embedded development :alien: A place where Developers and Teams have true Freedom! No more vendor lock-in!

    Project mention: Setting up a Web Server with ESP8266 | reddit.com/r/esp8266 | 2021-06-06

    I actually read the same thing few days ago on the platformio.org site. So thank you for mentioning that. But the concept and in fact even the API is the same. Just the underlying storage structure is different from what I gathered. So you can simply tell your code to use LittleFS instead of SPIFFS (including whatever uploads/creates the file system) and it will work. But if you have an existing file system which you don't want to overwrite, then it will cause issues. That last part probably not being an issue for people flashing their own boards, but for devices out in the wild (especially consumer products) over-the-air updates where the file system doesn't change would probably cause some issues.

  • GitHub repo john

    John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

    Project mention: Working on pulling the hash from a zip file to recover the password, zip2john is just dumping the file and giving me trash? | reddit.com/r/HowToHack | 2021-07-29

    Depending on the size of the files inside the zip it’s possible your large hash file is correct. See this link the BOM issue you’re having is an encoding issue. Convert the file from UTF8 BOM to just plain UTF8. The next issue you might run into is hashcat or John not liking the size of your hash file. I don’t have any good advice if you encounter that issue. ZIP hashes are known to be hard to work with.

  • GitHub repo openwifi

    open-source 802.11 WiFi baseband chip/FPGA design

    Project mention: How many more years until we have a completely open source RISC-V SOC? | reddit.com/r/RISCV | 2021-05-26
  • GitHub repo glasgow

    Scots Army Knife for electronics

    Project mention: How does USB device discovery work? [video] | news.ycombinator.com | 2021-07-11
  • GitHub repo NyuziProcessor

    GPGPU microprocessor architecture

    Project mention: Nyuzi – An Experimental Open-Source FPGA GPGPU Processor | reddit.com/r/patient_hackernews | 2021-02-14
  • GitHub repo cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    Project mention: XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 | reddit.com/r/RISCV | 2021-07-07

    Ariane is now cva6 (it moved to a industry supported non-profit).

  • GitHub repo VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

    Project mention: Tips on building a RISC-V processor on FPGA | reddit.com/r/RISCV | 2021-06-15
  • GitHub repo darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

    Project mention: Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux | reddit.com/r/linux | 2021-06-26

    Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.

  • GitHub repo clash-ghc

    Haskell to VHDL/Verilog/SystemVerilog compiler

    Project mention: Conway's Game of Life on FPGA | news.ycombinator.com | 2021-06-05

    I've been working with FPGAs for years (in hobby, at work I'm a mere "user" of them), and it always baffled me how poorly matched the imperative paradigm of Verilog and VHDL is to them.

    I think the idea was to make it look "familiar" to engineers by looking like C (Verilog) or Ada (VHDL). But FPGAs are nothing like CPUs, and what you end up instead is a whole lot of "common constructs" where you know how they will be synthesized in hardware. And worse: Practically no good way to do abstraction.

    Functional languages are a much, much better match, because that's what FPGAs are: Combining functions together. This works on higher orders as well, and it works well with polymorphism!

    So privately at least, for anything substantial I've since been using Clash, which is essentially a Haskell subset translated to Verilog or VHDL: https://clash-lang.org

    The learning curve is very steep, I think I'm only as effective as I am in it because I was already proficient in Haskell. But then the code is so enormously concise and modular, and I now have a small library of abstractions that I can just reuse (for example, adding AXI4 to my designs). It's a joy.

  • GitHub repo hdl

    HDL libraries and projects

    Project mention: Intel Quartus Version Control? | reddit.com/r/FPGA | 2021-02-21

    There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl

  • GitHub repo SpinalHDL

    Scala based HDL

    Project mention: Chisel/Firrtl Hardware Compiler Framework | news.ycombinator.com | 2021-07-05
  • GitHub repo Silice

    Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.

    Project mention: Silice: A language for hardcoding Algorithms into FPGA hardware | news.ycombinator.com | 2021-06-22
  • GitHub repo platformio-vscode-ide

    PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

    Project mention: VS Code update 1.56 breaks PlatformIO compile and upload functionality | reddit.com/r/arduino | 2021-05-19

    Thanks for the provided information. There is a reported issue https://github.com/platformio/platformio-vscode-ide/issues/2554 and we work on reproducing. Please follow issue #2554.

  • GitHub repo fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

    Project mention: Industry development process? | reddit.com/r/FPGA | 2021-02-10
  • GitHub repo zipcpu

    A small, light weight, RISC CPU soft core

    Project mention: What modules/hardware would you like to see? | reddit.com/r/FPGA | 2021-05-14

    I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.

  • GitHub repo cariboulite

    CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

    Project mention: What’s the best alternative to RTL that’s not TOO expensive but does TX/RX? There seems to be a lot of choices. | reddit.com/r/RTLSDR | 2021-07-25
  • GitHub repo uhd

    The USRP™ Hardware Driver Repository

    Project mention: USRP Low Band Center Frequency Shift | reddit.com/r/sdr | 2021-06-16
  • GitHub repo nmigen

    A refreshed Python toolbox for building complex digital hardware

    Project mention: Help a newbie | reddit.com/r/FPGA | 2021-06-07

    You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.

  • GitHub repo hls4ml

    Machine learning in FPGAs using HLS

    Project mention: FPGA Neural Network | reddit.com/r/FPGA | 2021-04-03

    We've been building an open-source system to do the translation from Keras/PyTorch/TensorFlow/ONNX to FPGA firmware (through HLS) for low-latency inference called hls4ml: https://github.com/fastmachinelearning/hls4ml

  • GitHub repo prjxray

    Documenting the Xilinx 7-series bit-stream format.

    Project mention: The J1 Forth CPU | news.ycombinator.com | 2021-01-14

    Here is a project to reverse engineer the Xilinx series 7 FPGAs to be able to target them with open source tools:

    https://github.com/SymbiFlow/prjxray

  • GitHub repo open-fpga-verilog-tutorial

    Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

    Project mention: What's the difference between FPGA, RISC-V, Arduino? | reddit.com/r/RISCV | 2021-04-22

    Among your choices, FPGA is the answer. I would suggest a cheap iCE40 board like the iCESugar, to get started. Then follow tutorials targetting ice40+open stack.

  • GitHub repo vunit

    VUnit is a unit testing framework for VHDL/SystemVerilog

    Project mention: How do you do automated testing of your HDL? | reddit.com/r/FPGA | 2021-06-16
  • GitHub repo Cores-SweRV

    SweRV EH1 core

    Project mention: Nvidia's ownership of ARM could drive customers to RISC-V, other alternatives if not careful, says Xilinx CEO | reddit.com/r/RISCV | 2021-05-20

    This act is probably the single biggest driver of immediate term adoption of RISC-V. Western Digital creating their own RISC-V chip and open sourcing it hurt either.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-07-29.

Index

What are some of the best open-source Fpga projects? This list will help you:

Project Stars
1 PlatformIO 5,246
2 john 5,136
3 openwifi 1,896
4 glasgow 1,451
5 NyuziProcessor 1,414
6 cva6 1,241
7 VexRiscv 1,191
8 darkriscv 1,149
9 clash-ghc 1,018
10 hdl 802
11 SpinalHDL 791
12 Silice 786
13 platformio-vscode-ide 741
14 fusesoc 705
15 zipcpu 698
16 cariboulite 630
17 uhd 582
18 nmigen 561
19 hls4ml 525
20 prjxray 509
21 open-fpga-verilog-tutorial 498
22 vunit 468
23 Cores-SweRV 456