Top 23 Fpga Open-Source Projects
PlatformIO is a professional collaborative platform for embedded development :alien: A place where Developers and Teams have true Freedom! No more vendor lock-in!Project mention: Setting up a Web Server with ESP8266 | reddit.com/r/esp8266 | 2021-06-06
I actually read the same thing few days ago on the platformio.org site. So thank you for mentioning that. But the concept and in fact even the API is the same. Just the underlying storage structure is different from what I gathered. So you can simply tell your code to use LittleFS instead of SPIFFS (including whatever uploads/creates the file system) and it will work. But if you have an existing file system which you don't want to overwrite, then it will cause issues. That last part probably not being an issue for people flashing their own boards, but for devices out in the wild (especially consumer products) over-the-air updates where the file system doesn't change would probably cause some issues.
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAsProject mention: Working on pulling the hash from a zip file to recover the password, zip2john is just dumping the file and giving me trash? | reddit.com/r/HowToHack | 2021-07-29
Depending on the size of the files inside the zip it’s possible your large hash file is correct. See this link the BOM issue you’re having is an encoding issue. Convert the file from UTF8 BOM to just plain UTF8. The next issue you might run into is hashcat or John not liking the size of your hash file. I don’t have any good advice if you encounter that issue. ZIP hashes are known to be hard to work with.
Scout APM: A developer's best friend. Try free for 14-days. Scout APM uses tracing logic that ties bottlenecks to source code so you know the exact line of code causing performance issues and can get back to building a great product faster.
open-source 802.11 WiFi baseband chip/FPGA designProject mention: How many more years until we have a completely open source RISC-V SOC? | reddit.com/r/RISCV | 2021-05-26
Scots Army Knife for electronicsProject mention: How does USB device discovery work? [video] | news.ycombinator.com | 2021-07-11
GPGPU microprocessor architectureProject mention: Nyuzi – An Experimental Open-Source FPGA GPGPU Processor | reddit.com/r/patient_hackernews | 2021-02-14
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting LinuxProject mention: XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 | reddit.com/r/RISCV | 2021-07-07
Ariane is now cva6 (it moved to a industry supported non-profit).
A FPGA friendly 32 bit RISC-V CPU implementationProject mention: Tips on building a RISC-V processor on FPGA | reddit.com/r/RISCV | 2021-06-15
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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!Project mention: Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux | reddit.com/r/linux | 2021-06-26
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
Haskell to VHDL/Verilog/SystemVerilog compilerProject mention: Conway's Game of Life on FPGA | news.ycombinator.com | 2021-06-05
I've been working with FPGAs for years (in hobby, at work I'm a mere "user" of them), and it always baffled me how poorly matched the imperative paradigm of Verilog and VHDL is to them.
I think the idea was to make it look "familiar" to engineers by looking like C (Verilog) or Ada (VHDL). But FPGAs are nothing like CPUs, and what you end up instead is a whole lot of "common constructs" where you know how they will be synthesized in hardware. And worse: Practically no good way to do abstraction.
Functional languages are a much, much better match, because that's what FPGAs are: Combining functions together. This works on higher orders as well, and it works well with polymorphism!
So privately at least, for anything substantial I've since been using Clash, which is essentially a Haskell subset translated to Verilog or VHDL: https://clash-lang.org
The learning curve is very steep, I think I'm only as effective as I am in it because I was already proficient in Haskell. But then the code is so enormously concise and modular, and I now have a small library of abstractions that I can just reuse (for example, adding AXI4 to my designs). It's a joy.
HDL libraries and projectsProject mention: Intel Quartus Version Control? | reddit.com/r/FPGA | 2021-02-21
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
Scala based HDLProject mention: Chisel/Firrtl Hardware Compiler Framework | news.ycombinator.com | 2021-07-05
Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.Project mention: Silice: A language for hardcoding Algorithms into FPGA hardware | news.ycombinator.com | 2021-06-22
PlatformIO IDE for VSCode: The next generation integrated development environment for IoTProject mention: VS Code update 1.56 breaks PlatformIO compile and upload functionality | reddit.com/r/arduino | 2021-05-19
Thanks for the provided information. There is a reported issue https://github.com/platformio/platformio-vscode-ide/issues/2554 and we work on reproducing. Please follow issue #2554.
Package manager and build abstraction tool for FPGA/ASIC developmentProject mention: Industry development process? | reddit.com/r/FPGA | 2021-02-10
A small, light weight, RISC CPU soft coreProject mention: What modules/hardware would you like to see? | reddit.com/r/FPGA | 2021-05-14
I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.
CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDRProject mention: What’s the best alternative to RTL that’s not TOO expensive but does TX/RX? There seems to be a lot of choices. | reddit.com/r/RTLSDR | 2021-07-25
The USRP™ Hardware Driver RepositoryProject mention: USRP Low Band Center Frequency Shift | reddit.com/r/sdr | 2021-06-16
A refreshed Python toolbox for building complex digital hardwareProject mention: Help a newbie | reddit.com/r/FPGA | 2021-06-07
You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.
Machine learning in FPGAs using HLSProject mention: FPGA Neural Network | reddit.com/r/FPGA | 2021-04-03
We've been building an open-source system to do the translation from Keras/PyTorch/TensorFlow/ONNX to FPGA firmware (through HLS) for low-latency inference called hls4ml: https://github.com/fastmachinelearning/hls4ml
Documenting the Xilinx 7-series bit-stream format.
Learn how to design digital systems and synthesize them into an FPGA using only opensource toolsProject mention: What's the difference between FPGA, RISC-V, Arduino? | reddit.com/r/RISCV | 2021-04-22
Among your choices, FPGA is the answer. I would suggest a cheap iCE40 board like the iCESugar, to get started. Then follow tutorials targetting ice40+open stack.
VUnit is a unit testing framework for VHDL/SystemVerilogProject mention: How do you do automated testing of your HDL? | reddit.com/r/FPGA | 2021-06-16
SweRV EH1 coreProject mention: Nvidia's ownership of ARM could drive customers to RISC-V, other alternatives if not careful, says Xilinx CEO | reddit.com/r/RISCV | 2021-05-20
This act is probably the single biggest driver of immediate term adoption of RISC-V. Western Digital creating their own RISC-V chip and open sourcing it hurt either.
What are some of the best open-source Fpga projects? This list will help you: