Asic

Top 23 Asic Open-Source Projects

  • skywater-pdk

    Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

    Project mention: Ask HN: Open-Source Simple CPU? | news.ycombinator.com | 2024-03-16

    Preferably Intel compatible or able to run Linux? Something I can build in my garage or in a simple microprocessor fab.

    https://github.com/google/skywater-pdk

  • cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    Project mention: CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux | news.ycombinator.com | 2023-11-15
  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  • neorv32

    :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24
  • clash-ghc

    Haskell to VHDL/Verilog/SystemVerilog compiler

    Project mention: Clash: A Functional Hardware Description Language | news.ycombinator.com | 2023-12-27
  • serv

    SERV - The SErial RISC-V CPU

    Project mention: SERV – The SErial RISC-V CPU | news.ycombinator.com | 2023-12-10
  • openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Project mention: [D][P] Represent Analog Circuits as Graphs | /r/MachineLearning | 2023-04-15

    I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.

  • riscv

    RISC-V CPU Core (RV32IM)

    Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

    I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  • axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  • biriscv

    32-bit Superscalar RISC-V CPU

    Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21
  • vunit

    VUnit is a unit testing framework for VHDL/SystemVerilog

  • gf180mcu-pdk

    PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

  • tensil

    Open source machine learning accelerators

    Project mention: Tensil | news.ycombinator.com | 2023-06-22
  • ara

    The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core (by pulp-platform)

    Project mention: x86 vs ARM; Vector and Matrix Extensions; How do they compare? | /r/hardware | 2023-12-09

    yeah, ara also currently doesn't work, but that it exist is already really cool, and will likely get fixed and completed in the future

  • esp

    Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

  • surf

    A huge VHDL library for FPGA development (by slaclab)

  • rggen

    Code generation tool for control and status registers

  • mempool

    A 256-RISC-V-core system with low-latency access into shared L1 memory. (by pulp-platform)

    Project mention: MemPool: Many-core image processor based on RISC-V with Shared L1 cache | news.ycombinator.com | 2023-04-11

    I don't get it:

    https://github.com/pulp-platform/mempool/blob/main/software/...

    How is that mapping to cores happening? I see indexing by core id for the multiply but how does it magically end up running on a specific core? Magic compiler?

  • systemrdl-compiler

    SystemRDL 2.0 language compiler front-end

  • livehd

    Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  • open-register-design-tool

    Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  • skillbridge

    A seamless python to Cadence Virtuoso Skill interface

  • neoTRNG

    🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

    Project mention: A really tiny and platform-independent true random number generator for FPGAs and ASICs | /r/cryptography | 2023-11-06
  • pygears

    HW Design: A Functional Approach

  • SaaSHub

    SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2024-03-16.

Asic related posts

Index

What are some of the best open-source Asic projects? This list will help you:

Project Stars
1 skywater-pdk 2,806
2 cva6 2,029
3 neorv32 1,390
4 clash-ghc 1,359
5 serv 1,228
6 openlane 1,139
7 riscv 1,040
8 axi 902
9 biriscv 749
10 vunit 674
11 gf180mcu-pdk 333
12 tensil 319
13 ara 296
14 esp 284
15 surf 277
16 rggen 274
17 mempool 224
18 systemrdl-compiler 220
19 livehd 195
20 open-register-design-tool 179
21 skillbridge 157
22 neoTRNG 145
23 pygears 142
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SaaSHub helps you find the best software and product alternatives
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