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swerv_eh1 reviews and mentions
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Arm IPO to kick off today with company valued at $54.5B
Western Digital announced an open source core ("SweRV") in 2019, so I assume they already use them now that we are a few years on from that announcement.
https://github.com/westerndigitalcorporation/swerv_eh1
https://news.ycombinator.com/item?id=25002448
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Apple Possibly Exploring Open-Source Alternative to ARM Architecture
It's confusing that RISC-V is so often describes as "open source". The specs (ISA + extensions) are open and free from patents (at least as far as we know). There are a large number of open source implementations available. Many of these, however, implement only a simple microcontroller-style RV32I core.
The cores available in "large" physical chips you can buy today (XuanTie C906 on the Allwinner D1 SoC, SiFive U54/74 e.g. on the BeagleV and HiFive Unmatched) are proprietary. I think one of the few companies that open sourced their commercially used cores is Western Digital ("swerv" cores - https://github.com/westerndigitalcorporation/swerv_eh1), but these are also RV32I microcontroller-class CPUs.
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A dedicated licence for open-source hardware: CERN OHL approved by OSI
There is a lot of open hardware.
See e.g.
https://ohwr.org/, https://opencores.org/
or https://github.com/westerndigitalcorporation/swerv_eh1_fpga https://github.com/westerndigitalcorporation/swerv_eh1
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A note from our sponsor - WorkOS
workos.com | 25 Apr 2024
Stats
westerndigitalcorporation/swerv_eh1 is an open source project licensed under Apache License 2.0 which is an OSI approved license.
The primary programming language of swerv_eh1 is SystemVerilog.
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