Rosebud

Framework for FPGA-accelerated Middlebox Development (by ucsdsysnet)

Rosebud Alternatives

Similar projects and alternatives to Rosebud

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better Rosebud alternative or higher similarity.

Rosebud reviews and mentions

Posts with mentions or reviews of Rosebud. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-29.
  • ASCII Comparison in VHDL
    1 project | /r/FPGA | 25 Dec 2022
    Here is a python script I wrote a while ago that takes a list of strings and generates verilog code for an efficient bit-split string matching implementation: https://github.com/ucsdsysnet/Shire/blob/master/fpga_src/accel/archive/sme/python/sme_rulecompiler.py
  • What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?
    4 projects | /r/FPGA | 29 Jun 2022
    Sure, I suppose trivial code might be somewhat readable. But doing something non-trivial is a different story. For example, this is what spinal HDL generates for vexriscv: https://github.com/ucsdsysnet/Shire/blob/master/fpga_src/lib/Shire/rtl/VexRiscv.v. This isn't exactly readable. There are about 320 _zz_ signals in there that presumably didn't exist in the original scala code.

Stats

Basic Rosebud repo stats
2
31
0.0
about 1 year ago

ucsdsysnet/Rosebud is an open source project licensed under MIT License which is an OSI approved license.

The primary programming language of Rosebud is Verilog.


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