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I also found this Forth implementation that might work.
as for designing, i used Digital to create the circuit and export it to Verilog, then Quartus II to synthese it for the MAX7000 series of CPLDs (because they are perfectly compatibile with the ATF150x series), then used POF2JED to convert the generated POF file into a JED file, which can finally be used in ATMISP to load onto the CPLD.
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