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The accelerator generator was developed in Chisel and we built our own parametrizable compiler to target it. The link in the post takes you to the documentation, and here's a link to the Github repository: https://github.com/tensil-ai/tensil/
Here is an example of deploying a basic ML application to an ICE40 using a custom Keras to NN generator https://github.com/edge-analytics/fpga-sleep-tracker
So it definitely can be done with some careful attention to the limited number of multipliers on the device. I’ll be curious to check out Tensil does in terms of mapping with highly resource constrained FPGAs. Looks like a very cool tool.