FPGA development live stream: 10G Ethernet on Intel Stratix 10 MX and DX

• corundum

  3 1,449 9.4 Verilog

  Open source FPGA-based NIC and platform for in-network compute

  

  For various reasons, I need to port corundum to run on Intel Stratix 10 MX and DX. As part of this process, I need to bring up both the PCIe and Ethernet interfaces on both of the cards. Also, even though both devices are Stratix 10, they use different tiles (H-tile on the MX vs. E-tile and P-tile on the DX) so the interface and capabilities are actually rather different. So, next week I'll run through the bring-up of a 10 Gbps link on both of these FPGAs by building example designs for verilog-ethernet. This will include setting up the H-tile and E-tile for operation at 10 Gbps as well as some debugging with both signaltap and the quartus "system console". If you want to learn a bit about how Intel FPGAs are put together, how 10G Ethernet works at the physical layer, and some of the techniques for debugging high speed serial links, be sure to tune in.

• verilog-ethernet

  2 1,888 8.8 Verilog

  Verilog Ethernet components for FPGA implementation

  For various reasons, I need to port corundum to run on Intel Stratix 10 MX and DX. As part of this process, I need to bring up both the PCIe and Ethernet interfaces on both of the cards. Also, even though both devices are Stratix 10, they use different tiles (H-tile on the MX vs. E-tile and P-tile on the DX) so the interface and capabilities are actually rather different. So, next week I'll run through the bring-up of a 10 Gbps link on both of these FPGAs by building example designs for verilog-ethernet. This will include setting up the H-tile and E-tile for operation at 10 Gbps as well as some debugging with both signaltap and the quartus "system console". If you want to learn a bit about how Intel FPGAs are put together, how 10G Ethernet works at the physical layer, and some of the techniques for debugging high speed serial links, be sure to tune in.

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