Glacial – microcoded RISC-V core designed for low FPGA resource utilization

• glacial

  1 72 0.0 Python

  Glacial - microcoded RISC-V core designed for low FPGA resource utilization

  I'm surprised that there aren't any specialised instructions or hardware resources to handle the RISC-V instruction decoding/dispatching. [1]

  Like, sure, it's not meant to be a fast implementation, but even just a "mask byte with 0x7C and set PC to that value times 8" instruction (which in an FPGA implementation is just rearranging the wires) could save 5-6 cycles per instruction.

  Is it really "microcoded" when all you're doing is writing a RISC-V emulator that runs on what looks to be a fairly standard 8 bit CPU?

  [1] https://github.com/brouhaha/glacial/blob/master/ucode/ucode....

• serv

  10 911 6.5 Verilog

  SERV - The SErial RISC-V CPU

  Along the same lines of minimizing the amount of logic used at the cost of cycles, there's SERV which uses a bit-serial implementation with a 1-bit data path: https://github.com/olofk/serv

  From time to time, I have been tempted to design a RISC-V implementation out of discrete TTL components. Sure, there are plenty of projects out there to build your own processor from scratch, but most of them aren't LLVM targets!

  The 32-bit datapaths and need for so many registers makes it a bit daunting to approach directly. That approach would probably end up similar in scale to a MIPS implementation I once saw done like that. (Can't find the link, but it was about half a dozen A4-sized PCBs).

  Retreating to an 8-bit microcoded approach and lifting all the registers and complexity into RAM and software is a very attractive idea. It's not like it would ever be a speed demon, either way.

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