Investigating Open Source RISC/V design for inclusion on FPGA

• taiga-project

  1 - -

• VexRiscv

  21 2,244 7.6 Assembly

  A FPGA friendly 32 bit RISC-V CPU implementation

  

I believe VexRiscv fits that description https://github.com/SpinalHDL/VexRiscv

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

• ibex

  20 1,237 8.5 SystemVerilog

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  

I'll put in a plug for Ibex https://github.com/lowRISC/ibex the core I work on. We don't optimise for FPGA so you may not meet 100 MHz out of the box (have been playing with improving FPGA frequency but no changes to share as of yet) the higher performance configurations can reach 3.13 CoreMark/MHz (and more with the branch predictor enabled, that's a bit less tested than the other configs so haven't put the number in the README, think it's more like 3.25 CoreMark/MHz).

Suggest a related project