Verilog pong-game

Open-source Verilog projects categorized as pong-game Edit details
Related topics: #Clash #Hardware #Haskell #Fpga

Verilog pong-game Projects

  • clash-pong

    Pong in Haskell / Clash, running as software using SDL and as hardware targeting FPGAs

    Project mention: Retrocomputing with Clash: Haskell for FPGA Hardware Design (book) | reddit.com/r/haskell | 2021-11-22

    However, all the code from the book (as collected at https://retrocla.sh/) synthesizes for real hardware FPGAs. I've been using a Nexys A7-50T (Xilinx 7-series FPGA) and old Papilio Pro (Xilinx 6-series) and Papilio One (Xilinx 3-series) FPGAs; the Nexys is my daily driver so all repos come with Shake rules for building for that. But people have also contributed support for the DECA Arrow (Intel MAX 10) and Terasic DE0-Nano (Intel Cyclone IV) to clash-pong, so you should be able to take that as a template if you want to use something else.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-11-22.

Index

Project Stars
1 clash-pong 4
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